From: Dinh Nguyen <dinguyen@kernel.org>
To: "Rabara, Niravkumar L" <niravkumar.l.rabara@intel.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: "Ng, Adrian Ho Yin" <adrian.ho.yin.ng@intel.com>,
"andrew@lunn.ch" <andrew@lunn.ch>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"krzysztof.kozlowski+dt@linaro.org"
<krzysztof.kozlowski+dt@linaro.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Turquette, Mike" <mturquette@baylibre.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"richardcochran@gmail.com" <richardcochran@gmail.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"wen.ping.teh@intel.com" <wen.ping.teh@intel.com>
Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock manager
Date: Sun, 6 Aug 2023 12:53:38 -0500 [thread overview]
Message-ID: <5b4bd1cd-ff2d-3aef-8e14-ec3b3c158864@kernel.org> (raw)
In-Reply-To: <DM6PR11MB3291627AB955685C345F7B71A20BA@DM6PR11MB3291.namprd11.prod.outlook.com>
On 8/2/23 02:14, Rabara, Niravkumar L wrote:
>
>
>> -----Original Message-----
>> From: Conor Dooley <conor.dooley@microchip.com>
>> Sent: Wednesday, 2 August, 2023 3:02 PM
>> To: Rabara, Niravkumar L <niravkumar.l.rabara@intel.com>
>> Cc: Ng, Adrian Ho Yin <adrian.ho.yin.ng@intel.com>; andrew@lunn.ch;
>> conor+dt@kernel.org; devicetree@vger.kernel.org; dinguyen@kernel.org;
>> krzysztof.kozlowski+dt@linaro.org; linux-clk@vger.kernel.org; linux-
>> kernel@vger.kernel.org; Turquette, Mike <mturquette@baylibre.com>;
>> netdev@vger.kernel.org; p.zabel@pengutronix.de;
>> richardcochran@gmail.com; robh+dt@kernel.org; sboyd@kernel.org;
>> wen.ping.teh@intel.com
>> Subject: Re: [PATCH v3 3/5] dt-bindings: clock: add Intel Agilex5 clock
>> manager
>>
>> On Wed, Aug 02, 2023 at 10:58:42AM +0800, niravkumar.l.rabara@intel.com
>> wrote:
>>> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>>>
>>> Add clock ID definitions for Intel Agilex5 SoCFPGA.
>>> The registers in Agilex5 handling the clock is named as clock manager.
>>>
>>> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
>>> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
>>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
>>
>> Damn, I was too late - you already sent a v3 :/
>>
>> However, there only seems to be a v3 of this one patch and it was sent in
>> reply to the v2 series? The normal thing to do is resend the entire series, not
>> just one patch, as a new thread. Not using a new thread may make it harder
>> to apply & will also bury the email in people's mailboxes that use things like
>> mutt. A single patch as a reply is also confusing, as the rest of the v3 looks like
>> it is missing!
>>
>> Thanks,
>> Conor.
>
> Sorry I made a mistake.
> Should I send out entire series with PATCH v3 subject? Or should I wait for review comment on remaining patches and then send entire series with rework and subject prefix PATCH v3?
>
No need to send out a V3. I've applied patches 1-3 and 5. Will give a
little more time for the clk patch.
Dinh
next prev parent reply other threads:[~2023-08-06 17:53 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-18 13:22 [PATCH 0/4] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-06-18 18:47 ` Krzysztof Kozlowski
2023-06-20 14:12 ` niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets niravkumar.l.rabara
2023-06-18 18:49 ` Krzysztof Kozlowski
2023-06-20 10:39 ` wen.ping.teh
2023-06-20 11:06 ` Krzysztof Kozlowski
2023-06-21 10:45 ` wen.ping.teh
2023-06-19 2:15 ` Rob Herring
2023-06-18 13:22 ` [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform niravkumar.l.rabara
2023-06-20 14:42 ` Dinh Nguyen
2023-06-18 13:22 ` [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA niravkumar.l.rabara
2023-06-18 18:56 ` Krzysztof Kozlowski
2023-06-20 14:07 ` niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-08-01 1:02 ` [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-08-01 20:53 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 niravkumar.l.rabara
2023-08-01 20:55 ` Conor Dooley
2023-08-01 1:02 ` [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager niravkumar.l.rabara
2023-08-01 20:57 ` Conor Dooley
2023-08-02 3:06 ` Rabara, Niravkumar L
2023-08-02 6:58 ` Conor Dooley
2023-08-02 2:58 ` [PATCH v3 " niravkumar.l.rabara
2023-08-02 7:02 ` Conor Dooley
2023-08-02 7:14 ` Rabara, Niravkumar L
2023-08-06 17:53 ` Dinh Nguyen [this message]
2023-08-06 19:35 ` [PATCH v2 " Krzysztof Kozlowski
2023-08-07 3:56 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 niravkumar.l.rabara
2023-08-08 11:03 ` Dinh Nguyen
2023-08-09 21:28 ` Stephen Boyd
2023-08-10 10:56 ` Dinh Nguyen
2023-08-09 21:26 ` Stephen Boyd
2023-08-13 12:53 ` Rabara, Niravkumar L
2023-08-14 2:48 ` Dinh Nguyen
2023-08-14 2:59 ` Rabara, Niravkumar L
2023-08-01 1:02 ` [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA niravkumar.l.rabara
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