[PATCH v2 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

[PATCH v2 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

This patch series extends PCIe Gen5/Gen6 support for the max-link-speed
property across device tree bindings and kernel validation logic.

With PCIe 6.0 now supported in the Linux kernel and industry IP providers
like Synopsys/Cadence offering PCIe 6.0-compatible IPs, existing device
tree bindings and checks for max-link-speed (limited to Gen1~Gen4) no
longer align with hardware capabilities.

Documentation updates:

Patch 1/3 extends the PCI host controller binding (pci-bus-common.yaml) to
explicitly include Gen5/Gen6.

Patch 2/3 updates the PCI endpoint binding (pci-ep.yaml) with the same
extension.

Kernel validation fix:

Patch 3/3 relaxes the max-link-speed check in of_pci_get_max_link_speed()
to accept values up to 6, ensuring compatibility with newer generations.

These changes ensure that device tree configurations for modern PCIe
controllers (e.g., Synopsys/Cadence IP-based designs) can fully utilize
Gen5/Gen6 speeds without DT validation errors.

---
In my impression, they have already obtained the relevant certifications.

e.g.:
Synopsys:
https://www.synopsys.com/dw/ipdir.php?ds=dwc_pcie6_controller

Cadence:
https://www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link/controller-for-pcie-and-cxl/controller-for-pcie.html
---

---
Changes for v2:
- The following files have been deleted:
  Documentation/devicetree/bindings/pci/pci.txt

  Update to this file again:
  dtschema/schemas/pci/pci-bus-common.yaml
---

Hans Zhang (3):
  dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6
  dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
  PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

 dtschema/schemas/pci/pci-bus-common.yaml          | 2 +-
 Documentation/devicetree/bindings/pci/pci.txt     | 5 +++--
 drivers/pci/of.c                                  | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)


base-commit: fee3e843b309444f48157e2188efa6818bae85cf
-- 
2.25.1

[PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Hans Zhang]

Update the device tree binding documentation for PCI to include
PCIe Gen5 and Gen6 support in the `max-link-speed` property.
The original documentation limited the value to 1~4 (Gen1~Gen4),
but the kernel now supports up to Gen6. This change ensures the
documentation aligns with the actual code implementation.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index ca97a00..413ef05 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -121,7 +121,7 @@ properties:
       unnecessary operation for unsupported link speed, for instance, trying to
       do training for unsupported link speed, etc.
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [ 1, 2, 3, 4 ]
+    enum: [ 1, 2, 3, 4, 5, 6 ]
 
   num-lanes:
     description: The number of PCIe lanes
-- 
2.25.1

[PATCH v2 2/3] dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6

[Hans Zhang]

Update the PCI Endpoint (EP) device tree binding documentation to
include PCIe Gen5 and Gen6 support for the `max-link-speed` property.
Similar to the Host Controller binding, the original EP binding
limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring
Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns
the EP binding with the kernel's PCIe 6.0 capabilities.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Hans Zhang <18255117159@163.com>
---
 Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml
index f75000e3093d..68aaad70b112 100644
--- a/Documentation/devicetree/bindings/pci/pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml
@@ -33,7 +33,7 @@ properties:
 
   max-link-speed:
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [ 1, 2, 3, 4 ]
+    enum: [ 1, 2, 3, 4, 5, 6]
 
   num-lanes:
     description: maximum number of lanes
-- 
2.25.1

[PATCH v2 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
This patch updates the validation in `of_pci_get_max_link_speed` to allow
values up to 6, ensuring compatibility with newer PCIe generations.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/of.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index ab7a8252bf41..379d90913937 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
 	u32 max_link_speed;
 
 	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
-	    max_link_speed == 0 || max_link_speed > 4)
+	    max_link_speed == 0 || max_link_speed > 6)
 		return -EINVAL;
 
 	return max_link_speed;
-- 
2.25.1

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Manivannan Sadhasivam]

On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
> Update the device tree binding documentation for PCI to include
> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
> The original documentation limited the value to 1~4 (Gen1~Gen4),
> but the kernel now supports up to Gen6. This change ensures the
> documentation aligns with the actual code implementation.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>  dtschema/schemas/pci/pci-bus-common.yaml | 2 +-

As Rob commented in v1, this file lives in dtschema project. So update it there:
https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml

- Mani

>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
> index ca97a00..413ef05 100644
> --- a/dtschema/schemas/pci/pci-bus-common.yaml
> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
> @@ -121,7 +121,7 @@ properties:
>        unnecessary operation for unsupported link speed, for instance, trying to
>        do training for unsupported link speed, etc.
>      $ref: /schemas/types.yaml#/definitions/uint32
> -    enum: [ 1, 2, 3, 4 ]
> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>  
>    num-lanes:
>      description: The number of PCIe lanes
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

[Manivannan Sadhasivam]

On Thu, May 29, 2025 at 10:10:23AM +0800, Hans Zhang wrote:
> This patch series extends PCIe Gen5/Gen6 support for the max-link-speed
> property across device tree bindings and kernel validation logic.
> 
> With PCIe 6.0 now supported in the Linux kernel and industry IP providers
> like Synopsys/Cadence offering PCIe 6.0-compatible IPs, existing device
> tree bindings and checks for max-link-speed (limited to Gen1~Gen4) no
> longer align with hardware capabilities.
> 
> Documentation updates:
> 
> Patch 1/3 extends the PCI host controller binding (pci-bus-common.yaml) to
> explicitly include Gen5/Gen6.
> 
> Patch 2/3 updates the PCI endpoint binding (pci-ep.yaml) with the same
> extension.
> 
> Kernel validation fix:
> 
> Patch 3/3 relaxes the max-link-speed check in of_pci_get_max_link_speed()
> to accept values up to 6, ensuring compatibility with newer generations.
> 
> These changes ensure that device tree configurations for modern PCIe
> controllers (e.g., Synopsys/Cadence IP-based designs) can fully utilize
> Gen5/Gen6 speeds without DT validation errors.
> 
> ---
> In my impression, they have already obtained the relevant certifications.
> 
> e.g.:
> Synopsys:
> https://www.synopsys.com/dw/ipdir.php?ds=dwc_pcie6_controller
> 
> Cadence:
> https://www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link/controller-for-pcie-and-cxl/controller-for-pcie.html
> ---
> 
> ---
> Changes for v2:
> - The following files have been deleted:
>   Documentation/devicetree/bindings/pci/pci.txt
> 
>   Update to this file again:
>   dtschema/schemas/pci/pci-bus-common.yaml
> ---
> 
> Hans Zhang (3):
>   dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6
>   dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6

Applied patch 2 to pci/dt-bindings, thanks!

- Mani

>   PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6
> 
>  dtschema/schemas/pci/pci-bus-common.yaml          | 2 +-
>  Documentation/devicetree/bindings/pci/pci.txt     | 5 +++--
>  drivers/pci/of.c                                  | 2 +-
>  3 files changed, 5 insertions(+), 4 deletions(-)
> 
> 
> base-commit: fee3e843b309444f48157e2188efa6818bae85cf
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Manivannan Sadhasivam]

On Thu, May 29, 2025 at 10:10:26AM +0800, Hans Zhang wrote:
> The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
> This patch updates the validation in `of_pci_get_max_link_speed` to allow
> values up to 6, ensuring compatibility with newer PCIe generations.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>

DT binding validation should be sufficient. But still...

Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>

- Mani

> ---
>  drivers/pci/of.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index ab7a8252bf41..379d90913937 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
>  	u32 max_link_speed;
>  
>  	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
> -	    max_link_speed == 0 || max_link_speed > 4)
> +	    max_link_speed == 0 || max_link_speed > 6)
>  		return -EINVAL;
>  
>  	return max_link_speed;
> -- 
> 2.25.1
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Hans Zhang]

On 2025/6/18 00:45, Manivannan Sadhasivam wrote:
> On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
>> Update the device tree binding documentation for PCI to include
>> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
>> The original documentation limited the value to 1~4 (Gen1~Gen4),
>> but the kernel now supports up to Gen6. This change ensures the
>> documentation aligns with the actual code implementation.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>>   dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
> 
> As Rob commented in v1, this file lives in dtschema project. So update it there:
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml
> 

Dear Mani,

I made the patch based on the latest dtschema code pulled from github.

Also, I saw similar submissions as follows:
https://lore.kernel.org/linux-pci/advhonmqnxm4s6r3cl7ll5y3jfc566fcjvetvlzvy7bztzetev@t75xmo5fktde/

I don't know if Rob obtained this patch from here and then applied it to 
the dtschema project? Is there still a special process to submit this patch?


Dear Rob,

Can you apply this patch directly to the dtschema project?

Best regards,
Hans

> - Mani
> 
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
>> index ca97a00..413ef05 100644
>> --- a/dtschema/schemas/pci/pci-bus-common.yaml
>> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
>> @@ -121,7 +121,7 @@ properties:
>>         unnecessary operation for unsupported link speed, for instance, trying to
>>         do training for unsupported link speed, etc.
>>       $ref: /schemas/types.yaml#/definitions/uint32
>> -    enum: [ 1, 2, 3, 4 ]
>> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>>   
>>     num-lanes:
>>       description: The number of PCIe lanes
>> -- 
>> 2.25.1
>>
> 

Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

On 2025/6/18 00:50, Manivannan Sadhasivam wrote:
> On Thu, May 29, 2025 at 10:10:26AM +0800, Hans Zhang wrote:
>> The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
>> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
>> This patch updates the validation in `of_pci_get_max_link_speed` to allow
>> values up to 6, ensuring compatibility with newer PCIe generations.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
> 
> DT binding validation should be sufficient. But still...
> 
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
> 

Dear Mani，

Thank you very much for your review.

Best regards,
Hans


> - Mani
> 
>> ---
>>   drivers/pci/of.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
>> index ab7a8252bf41..379d90913937 100644
>> --- a/drivers/pci/of.c
>> +++ b/drivers/pci/of.c
>> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
>>   	u32 max_link_speed;
>>   
>>   	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
>> -	    max_link_speed == 0 || max_link_speed > 4)
>> +	    max_link_speed == 0 || max_link_speed > 6)
>>   		return -EINVAL;
>>   
>>   	return max_link_speed;
>> -- 
>> 2.25.1
>>
> 

Re: [PATCH v2 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Hans Zhang]

On 2025/6/18 22:22, Hans Zhang wrote:
> 
> 
> On 2025/6/18 00:45, Manivannan Sadhasivam wrote:
>> On Thu, May 29, 2025 at 10:10:24AM +0800, Hans Zhang wrote:
>>> Update the device tree binding documentation for PCI to include
>>> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
>>> The original documentation limited the value to 1~4 (Gen1~Gen4),
>>> but the kernel now supports up to Gen6. This change ensures the
>>> documentation aligns with the actual code implementation.
>>>
>>> Signed-off-by: Hans Zhang <18255117159@163.com>
>>> ---
>>>   dtschema/schemas/pci/pci-bus-common.yaml | 2 +-
>>
>> As Rob commented in v1, this file lives in dtschema project. So update 
>> it there:
>> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/pci/pci-bus-common.yaml
>>
> 
> Dear Mani,
> 
> I made the patch based on the latest dtschema code pulled from github.
> 
> Also, I saw similar submissions as follows:
> https://lore.kernel.org/linux-pci/advhonmqnxm4s6r3cl7ll5y3jfc566fcjvetvlzvy7bztzetev@t75xmo5fktde/
> 
> I don't know if Rob obtained this patch from here and then applied it to 
> the dtschema project? Is there still a special process to submit this 
> patch?
> 
> 
> Dear Rob,
> 
> Can you apply this patch directly to the dtschema project?
> 

Dear Rob,

Gentle ping.

Best regards,
Hans

> Best regards,
> Hans
> 
>> - Mani
>>
>>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/dtschema/schemas/pci/pci-bus-common.yaml 
>>> b/dtschema/schemas/pci/pci-bus-common.yaml
>>> index ca97a00..413ef05 100644
>>> --- a/dtschema/schemas/pci/pci-bus-common.yaml
>>> +++ b/dtschema/schemas/pci/pci-bus-common.yaml
>>> @@ -121,7 +121,7 @@ properties:
>>>         unnecessary operation for unsupported link speed, for 
>>> instance, trying to
>>>         do training for unsupported link speed, etc.
>>>       $ref: /schemas/types.yaml#/definitions/uint32
>>> -    enum: [ 1, 2, 3, 4 ]
>>> +    enum: [ 1, 2, 3, 4, 5, 6 ]
>>>     num-lanes:
>>>       description: The number of PCIe lanes
>>> -- 
>>> 2.25.1
>>>
>>

Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

Dear Bjorn,

Gentle ping.

Best regards,
Hans

On 2025/5/29 10:10, Hans Zhang wrote:
> The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
> This patch updates the validation in `of_pci_get_max_link_speed` to allow
> values up to 6, ensuring compatibility with newer PCIe generations.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>   drivers/pci/of.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index ab7a8252bf41..379d90913937 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
>   	u32 max_link_speed;
>   
>   	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
> -	    max_link_speed == 0 || max_link_speed > 4)
> +	    max_link_speed == 0 || max_link_speed > 6)
>   		return -EINVAL;
>   
>   	return max_link_speed;