From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Yaroslav Bolyukin" <iam@lach.pw>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org,
"Yaroslav Bolyukin" <iam@lach.pw>
Subject: Re: [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays
Date: Wed, 26 Nov 2025 16:10:34 +0200 [thread overview]
Message-ID: <5be6faede273533b88e592bd25776b639d2eeb9f@intel.com> (raw)
In-Reply-To: <20251126065126.54016-4-iam@lach.pw>
On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
> As per DisplayID v2.1a spec:
> If Offset 06h[2:0] is programmed to 001b (External DisplayPort), this
> field shall be cleared to 00b (Not supported).
>
> Link: https://lore.kernel.org/lkml/3abc1087618c822e5676e67a3ec2e64e506dc5ec@intel.com/
> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
> ---
> drivers/gpu/drm/drm_displayid_internal.h | 4 +++
> drivers/gpu/drm/drm_edid.c | 36 +++++++++++++++---------
> 2 files changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h
> index 5b1b32f73516..72f107ae832f 100644
> --- a/drivers/gpu/drm/drm_displayid_internal.h
> +++ b/drivers/gpu/drm/drm_displayid_internal.h
> @@ -142,9 +142,13 @@ struct displayid_formula_timing_block {
> struct displayid_formula_timings_9 timings[];
> } __packed;
>
> +#define DISPLAYID_VESA_DP_TYPE GENMASK(2, 0)
> #define DISPLAYID_VESA_MSO_OVERLAP GENMASK(3, 0)
> #define DISPLAYID_VESA_MSO_MODE GENMASK(6, 5)
>
> +#define DISPLAYID_VESA_DP_TYPE_EDP 0
> +#define DISPLAYID_VESA_DP_TYPE_DP 1
> +
> struct displayid_vesa_vendor_specific_block {
> struct displayid_block base;
> u8 oui[3];
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index a52fd6de9327..348aa31aea1b 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -6533,6 +6533,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
> struct displayid_vesa_vendor_specific_block *vesa =
> (struct displayid_vesa_vendor_specific_block *)block;
> struct drm_display_info *info = &connector->display_info;
> + int dp_type;
>
> if (block->num_bytes < 3) {
> drm_dbg_kms(connector->dev,
> @@ -6551,20 +6552,29 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
> return;
> }
>
> - switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> - default:
> - drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> + dp_type = FIELD_GET(DISPLAYID_VESA_DP_TYPE, vesa->data_structure_type);
> + if (dp_type > 1) {
> + drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved dp type value\n",
> connector->base.id, connector->name);
> - fallthrough;
> - case 0:
> - info->mso_stream_count = 0;
> - break;
> - case 1:
> - info->mso_stream_count = 2; /* 2 or 4 links */
> - break;
> - case 2:
> - info->mso_stream_count = 4; /* 4 links */
> - break;
> + }
> +
> + /* MSO is not supported for eDP */
> + if (dp_type != DISPLAYID_VESA_DP_TYPE_EDP) {
MSO is *only* supported on eDP, not the other way round!
BR,
Jani.
> + switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
> + default:
> + drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
> + connector->base.id, connector->name);
> + fallthrough;
> + case 0:
> + info->mso_stream_count = 0;
> + break;
> + case 1:
> + info->mso_stream_count = 2; /* 2 or 4 links */
> + break;
> + case 2:
> + info->mso_stream_count = 4; /* 4 links */
> + break;
> + }
> }
>
> if (info->mso_stream_count) {
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-11-26 14:10 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 6:51 [PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value Yaroslav Bolyukin
2025-11-26 6:51 ` [PATCH v6 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-11-26 9:05 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-11-26 9:13 ` Jani Nikula
2025-11-26 14:08 ` Jani Nikula
2025-11-26 14:50 ` Yaroslav
2025-11-26 14:59 ` Jani Nikula
2025-11-26 15:06 ` Yaroslav
2025-11-26 15:26 ` Yaroslav
2025-11-26 16:32 ` Jani Nikula
2025-11-26 14:20 ` Yaroslav
2025-11-26 14:29 ` Jani Nikula
2025-11-26 14:41 ` Yaroslav
2025-11-26 14:47 ` Jani Nikula
2025-11-26 14:53 ` Yaroslav
2025-11-26 6:51 ` [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-11-26 14:10 ` Jani Nikula [this message]
2025-11-26 14:22 ` Yaroslav
2025-11-26 6:51 ` [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-11-26 14:19 ` Jani Nikula
2025-11-26 14:35 ` Yaroslav
2025-11-26 14:52 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-11-26 14:20 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-11-26 14:25 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
2025-11-26 7:13 ` [PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value Yaroslav
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