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Sun, 08 Jan 2023 09:38:34 -0800 (PST) X-Google-Smtp-Source: AMrXdXs8XML+gYNBuoTC6l6oUvO1lDn1E1It03N6XT+5yMwdlbQ8IGFTStMzOSvIv+eI/F20YPTC1w== X-Received: by 2002:a17:907:6e16:b0:7c0:9f6f:6d8 with SMTP id sd22-20020a1709076e1600b007c09f6f06d8mr68968950ejc.2.1673199514359; Sun, 08 Jan 2023 09:38:34 -0800 (PST) Received: from starship ([89.237.103.62]) by smtp.gmail.com with ESMTPSA id sb25-20020a1709076d9900b007b2a58e31dasm2703474ejc.145.2023.01.08.09.38.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Jan 2023 09:38:33 -0800 (PST) Message-ID: <5dbe58d89f8a65ecfebdaf5cb263b9b4e359ce55.camel@redhat.com> Subject: Re: [PATCH 4/6] KVM: x86: Split out logic to generate "readable" APIC regs mask to helper From: Maxim Levitsky To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Marc Orr , Ben Gardon , Venkatesh Srinivas Date: Sun, 08 Jan 2023 19:38:32 +0200 In-Reply-To: <20230107011025.565472-5-seanjc@google.com> References: <20230107011025.565472-1-seanjc@google.com> <20230107011025.565472-5-seanjc@google.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.36.5 (3.36.5-2.fc32) MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 2023-01-07 at 01:10 +0000, Sean Christopherson wrote: > Move the generation of the readable APIC regs bitmask to a standalone > helper so that VMX can use the mask for its MSR interception bitmaps. > > No functional change intended. > > Signed-off-by: Sean Christopherson > --- > arch/x86/kvm/lapic.c | 34 +++++++++++++++++++++------------- > arch/x86/kvm/lapic.h | 2 ++ > 2 files changed, 23 insertions(+), 13 deletions(-) > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c > index c49b13418638..19697fe9b2c7 100644 > --- a/arch/x86/kvm/lapic.c > +++ b/arch/x86/kvm/lapic.c > @@ -1529,12 +1529,9 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) > #define APIC_REGS_MASK(first, count) \ > (APIC_REG_MASK(first) * ((1ull << (count)) - 1)) > > -static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, > - void *data) > +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic) > { > - unsigned char alignment = offset & 0xf; > - u32 result; > - /* this bitmask has a bit cleared for each reserved register */ > + /* Leave bits '0' for reserved and write-only registers. */ > u64 valid_reg_mask = > APIC_REG_MASK(APIC_ID) | > APIC_REG_MASK(APIC_LVR) | > @@ -1560,22 +1557,33 @@ static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, > if (kvm_lapic_lvt_supported(apic, LVT_CMCI)) > valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI); > > - /* > - * ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. WARN if KVM > - * reads ICR in x2APIC mode as it's an 8-byte register in x2APIC and > - * needs to be manually handled by the caller. > - */ > + /* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */ > if (!apic_x2apic_mode(apic)) > valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI) | > APIC_REG_MASK(APIC_DFR) | > APIC_REG_MASK(APIC_ICR2); > - else > - WARN_ON_ONCE(offset == APIC_ICR); > + > + return valid_reg_mask; > +} > +EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask); > + > +static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, > + void *data) > +{ > + unsigned char alignment = offset & 0xf; > + u32 result; > + > + /* > + * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in > + * x2APIC and needs to be manually handled by the caller. > + */ > + WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR); > > if (alignment + len > 4) > return 1; > > - if (offset > 0x3f0 || !(valid_reg_mask & APIC_REG_MASK(offset))) > + if (offset > 0x3f0 || > + !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) > return 1; > > result = __apic_read(apic, offset & ~0xf); > diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h > index df316ede7546..0a0ea4b5dd8c 100644 > --- a/arch/x86/kvm/lapic.h > +++ b/arch/x86/kvm/lapic.h > @@ -146,6 +146,8 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); > int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len); > void kvm_lapic_exit(void); > > +u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic); > + > #define VEC_POS(v) ((v) & (32 - 1)) > #define REG_POS(v) (((v) >> 5) << 4) > Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky