From: <Tudor.Ambarus@microchip.com>
To: <masonccyang@mxic.com.tw>, <broonie@kernel.org>,
<miquel.raynal@bootlin.com>, <richard@nod.at>, <vigneshr@ti.com>,
<boris.brezillon@collabora.com>, <matthias.bgg@gmail.com>
Cc: <juliensu@mxic.com.tw>, <linux-kernel@vger.kernel.org>,
<linux-spi@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
<p.yadav@ti.com>, <ycllin@mxic.com.tw>
Subject: Re: [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from BFPT
Date: Tue, 27 Oct 2020 16:57:38 +0000 [thread overview]
Message-ID: <5df6d950-d47e-daec-cd06-d6a1880457e7@microchip.com> (raw)
In-Reply-To: <1590737775-4798-2-git-send-email-masonccyang@mxic.com.tw>
Hi, Mason, YC Lin,
On 5/29/20 10:36 AM, Mason Yang wrote:
> Get maximum operation speed of device in octal mode from
> BFPT 20th DWORD.
>
I would like to understand how would we use the max speed value
at the SPI NOR level. The maximum operation speed is typically used
to determine the number of dummy cycles, which is described in xSPI
Spec for speeds of 200 MHz or less. Even if BFPT[dword20] describes
supported speeds up to 400 MHz, it doesn't indicate the number of
required dummy cycles. What number of dummy cycles would we use for
speeds higher than 200 MHz?
We may be tempted however to pass the max_speed_hz to the SPIMEM layer,
so that the controller can sync with the memory to choose the best
available speed.
Cheers,
ta
> Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
> ---
> drivers/mtd/spi-nor/core.h | 2 ++
> drivers/mtd/spi-nor/sfdp.c | 36 ++++++++++++++++++++++++++++++++++++
> drivers/mtd/spi-nor/sfdp.h | 4 ++++
> 3 files changed, 42 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index 6f2f6b2..7a36b22 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -190,6 +190,7 @@ struct spi_nor_locking_ops {
> *
> * @size: the flash memory density in bytes.
> * @page_size: the page size of the SPI NOR flash memory.
> + * @octal_max_speed: maximum operation speed of device in octal mode.
> * @hwcaps: describes the read and page program hardware
> * capabilities.
> * @reads: read capabilities ordered by priority: the higher index
> @@ -212,6 +213,7 @@ struct spi_nor_locking_ops {
> struct spi_nor_flash_parameter {
> u64 size;
> u32 page_size;
> + u16 octal_max_speed;
>
> struct spi_nor_hwcaps hwcaps;
> struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
> diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
> index f6038d3..4d13f66 100644
> --- a/drivers/mtd/spi-nor/sfdp.c
> +++ b/drivers/mtd/spi-nor/sfdp.c
> @@ -4,6 +4,7 @@
> * Copyright (C) 2014, Freescale Semiconductor, Inc.
> */
>
> +#include <linux/bitfield.h>
> #include <linux/slab.h>
> #include <linux/sort.h>
> #include <linux/mtd/spi-nor.h>
> @@ -26,6 +27,12 @@
> #define SFDP_JESD216A_MINOR 5
> #define SFDP_JESD216B_MINOR 6
>
> +/* Basic Flash Parameter Table 20th DWORD, Max operation speed of device */
> +struct octal_max_speed {
> + u8 idx; /* Bits value */
> + u16 hz; /* MHz */
> +};
> +
> struct sfdp_header {
> u32 signature; /* Ox50444653U <=> "SFDP" */
> u8 minor;
> @@ -440,6 +447,22 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> u32 addr;
> u16 half;
> u8 erase_mask;
> + static const struct octal_max_speed max_hz[] = {
> + /* Bits value, MHz */
> + { 0x0c, 400 },
> + { 0x0b, 333 },
> + { 0x0a, 266 },
> + { 0x09, 250 },
> + { 0x08, 200 },
> + { 0x07, 166 },
> + { 0x06, 133 },
> + { 0x05, 100 },
> + { 0x04, 80 },
> + { 0x03, 66 },
> + { 0x02, 50 },
> + { 0x01, 33 },
> + };
> + u8 idx;
>
> /* JESD216 Basic Flash Parameter Table length is at least 9 DWORDs. */
> if (bfpt_header->length < BFPT_DWORD_MAX_JESD216)
> @@ -604,6 +627,19 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
> return -EINVAL;
> }
>
> + /* Octal mode max speed */
> + idx = max(FIELD_GET(BFPT_DWORD20_OCTAL_DTR_MAX_SPEED,
> + bfpt.dwords[BFPT_DWORD(20)]),
> + FIELD_GET(BFPT_DWORD20_OCTAL_STR_MAX_SPEED,
> + bfpt.dwords[BFPT_DWORD(20)]));
> +
> + for (i = 0; i < ARRAY_SIZE(max_hz); i++) {
> + if (max_hz[i].idx == idx) {
> + params->octal_max_speed = max_hz[i].hz;
> + break;
> + }
> + }
> +
> return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt, params);
> }
>
> diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
> index e0a8ded..8ae6d9a 100644
> --- a/drivers/mtd/spi-nor/sfdp.h
> +++ b/drivers/mtd/spi-nor/sfdp.h
> @@ -83,6 +83,10 @@ struct sfdp_bfpt {
> #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
> #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
>
> +#define BFPT_DWORD20_OCTAL_MAX_SPEED_MASK GENMASK(31, 16)
> +#define BFPT_DWORD20_OCTAL_DTR_MAX_SPEED GENMASK(31, 28)
> +#define BFPT_DWORD20_OCTAL_STR_MAX_SPEED GENMASK(19, 16)
> +
> struct sfdp_parameter_header {
> u8 id_lsb;
> u8 minor;
>
next prev parent reply other threads:[~2020-10-27 16:58 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 7:36 [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Mason Yang
2020-05-29 7:36 ` [PATCH v4 1/7] mtd: spi-nor: sfdp: get octal mode maximum speed from BFPT Mason Yang
2020-05-29 9:23 ` Pratyush Yadav
2020-06-02 6:32 ` masonccyang
2020-07-13 5:49 ` masonccyang
2020-10-27 16:57 ` Tudor.Ambarus [this message]
2020-05-29 7:36 ` [PATCH v4 2/7] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Mason Yang
2020-05-29 9:27 ` Pratyush Yadav
2020-07-13 5:52 ` masonccyang
2020-10-27 17:19 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 3/7] mtd: spi-nor: sfdp: parse command sequences to change octal DTR mode Mason Yang
2020-07-13 5:55 ` masonccyang
2020-10-28 9:45 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 4/7] mtd: spi-nor: core: add configuration register 2 read & write support Mason Yang
2020-07-13 5:56 ` masonccyang
2020-10-28 10:18 ` Tudor.Ambarus
2020-05-29 7:36 ` [PATCH v4 5/7] mtd: spi-nor: core: execute command sequences to change octal DTR mode Mason Yang
2020-07-13 5:57 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 6/7] spi: mxic: patch for octal DTR mode support Mason Yang
2020-07-13 5:58 ` masonccyang
2020-05-29 7:36 ` [PATCH v4 7/7] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g Mason Yang
2020-05-29 9:42 ` Pratyush Yadav
2020-06-02 6:44 ` masonccyang
2020-06-03 5:53 ` Pratyush Yadav
2020-06-05 2:53 ` masonccyang
2020-06-05 7:47 ` Pratyush Yadav
2020-07-13 5:59 ` masonccyang
2020-10-28 10:25 ` Tudor.Ambarus
2020-05-29 9:13 ` [PATCH v4 0/7] mtd: spi-nor: add xSPI Octal DTR support Pratyush Yadav
2020-07-13 5:47 ` masonccyang
2020-10-28 10:42 ` Tudor.Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5df6d950-d47e-daec-cd06-d6a1880457e7@microchip.com \
--to=tudor.ambarus@microchip.com \
--cc=boris.brezillon@collabora.com \
--cc=broonie@kernel.org \
--cc=juliensu@mxic.com.tw \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=masonccyang@mxic.com.tw \
--cc=matthias.bgg@gmail.com \
--cc=miquel.raynal@bootlin.com \
--cc=p.yadav@ti.com \
--cc=richard@nod.at \
--cc=vigneshr@ti.com \
--cc=ycllin@mxic.com.tw \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox