From: Sodagudi Prasad <psodagud@codeaurora.org>
To: marc.zyngier@arm.com, sudeep.holla@arm.com, will.deacon@arm.com
Cc: Jason Cooper <jason@lakedaemon.net>,
Thomas Gleixner <tglx@linutronix.de>,
linux-kernel@vger.kernel.org
Subject: gic_write_grpen1 in hotplug flow
Date: Wed, 03 May 2017 18:30:04 -0700 [thread overview]
Message-ID: <5e16d564fc1f3482d9ee15a5a1df4265@codeaurora.org> (raw)
Hi All,
This is regarding the usage of gic_write_grpen1 API usage in irq-gic-v3
driver.
Here my understanding about ICC_IGRPEN1_EL1.
ICC_IGRPEN1_EL1 is banked between secure and non-secure states. If two
secure states are implemented, Secure side Group bit is set by the
platform firmware (PSCI) and kernel need to set in non secure state.
https://mail.codeaurora.org/?_task=mail&_action=compose&_id=676833541590a775943df6#
1) Currently gic_write_grpen1(0) is getting called from
gic_cpu_pm_notifier() for CPU_PM_ENTER in single security state only.
But enabling of group1 non-secure interrupts are done in CPU_PM_EXIT
path unconditionally. Why are we not disabling group1 non-secure
interrupts unconditionally in CPU_PM_ENTER(and disabling only in single
security state)?
2) Why group1 non-secure interrupts are not disabled in kernel during
cpu hotplug path? Spurious interrupt can still come if we dont disable
group1 non-secure interrupts, right?
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum,
Linux Foundation Collaborative Project
next reply other threads:[~2017-05-04 1:30 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-04 1:30 Sodagudi Prasad [this message]
2017-05-04 9:17 ` gic_write_grpen1 in hotplug flow Sudeep Holla
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