From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932355AbdEDBaL (ORCPT ); Wed, 3 May 2017 21:30:11 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42806 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932169AbdEDBaF (ORCPT ); Wed, 3 May 2017 21:30:05 -0400 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Wed, 03 May 2017 18:30:04 -0700 From: Sodagudi Prasad To: marc.zyngier@arm.com, sudeep.holla@arm.com, will.deacon@arm.com Cc: Jason Cooper , Thomas Gleixner , linux-kernel@vger.kernel.org Subject: gic_write_grpen1 in hotplug flow Message-ID: <5e16d564fc1f3482d9ee15a5a1df4265@codeaurora.org> User-Agent: Roundcube Webmail/1.2.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, This is regarding the usage of gic_write_grpen1 API usage in irq-gic-v3 driver. Here my understanding about ICC_IGRPEN1_EL1. ICC_IGRPEN1_EL1 is banked between secure and non-secure states. If two secure states are implemented, Secure side Group bit is set by the platform firmware (PSCI) and kernel need to set in non secure state. https://mail.codeaurora.org/?_task=mail&_action=compose&_id=676833541590a775943df6# 1) Currently gic_write_grpen1(0) is getting called from gic_cpu_pm_notifier() for CPU_PM_ENTER in single security state only. But enabling of group1 non-secure interrupts are done in CPU_PM_EXIT path unconditionally. Why are we not disabling group1 non-secure interrupts unconditionally in CPU_PM_ENTER(and disabling only in single security state)? 2) Why group1 non-secure interrupts are not disabled in kernel during cpu hotplug path? Spurious interrupt can still come if we dont disable group1 non-secure interrupts, right? -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project