From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 149FC3EDABB for ; Thu, 7 May 2026 12:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778157106; cv=none; b=dT+Q4XSM9dOCyAyh1M0XlD+JkkJ4tdtgOspQlk8bjP1p9cB7LRZDzNouFqVeFcFnPDHOftSmHcTN5PGczfxCrJcBJoT8yUt+jDmCZqTA2jfr4aU81hwf3A7SB/1To8q/H8PdhF6h00eBMU6sdhFJf2esnV6FxJb0hmsclpPZefQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778157106; c=relaxed/simple; bh=abR33LWqDOSHmYqXKopX4dV7qJgCLnKBEHLiDWopmKM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=OcxHEIOeOE5OJeZKv+gke8wIvXRxA+pTbXvQ5lMd4Kt+PQAzKZIVL2KBcmOv4DssgUgzvMe0Ni/9neCb7RuehsA11JyUfJYmvZ4TNMhcYDQXiiJyycVxkMYjTkO6SEjY6tJl5m7VK3El+WQu8dlD4+ImEPHAzyfDzR2iiH6gqns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=M/iP/65X; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="M/iP/65X" Message-ID: <5e9b15c7-5db4-408e-a5bc-75fe5752ed74@linux.dev> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1778157090; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cVcapITppFjdbgWyCIsD7Di3H3M7df4fmIK75pLRWfs=; b=M/iP/65XiomV/0Vr3DDPkszg7lw61MMKsk0KljW6BdM85buVlKRed8fdzcUtbfUkpvMdkg Wne3gpPVMexad+izAogv8xzH/34Ik/w8n72PvHFK1T2PyQaN3HBvIj8n0BmTKeVqoRrl4c VzIT85gl9FPSaSGvhY8yk75NX/VATdo= Date: Thu, 7 May 2026 13:30:55 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH net-next v3 1/4] net: rnpgbe: Add interrupt handling To: Dong Yibo , andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, danishanwar@ti.com, horms@kernel.org Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, yaojun@mucse.com References: <20260507081539.171844-1-dong100@mucse.com> <20260507081539.171844-2-dong100@mucse.com> Content-Language: en-US X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Vadim Fedorenko In-Reply-To: <20260507081539.171844-2-dong100@mucse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Migadu-Flow: FLOW_OUT On 07/05/2026 09:15, Dong Yibo wrote: > Add comprehensive interrupt handling for the RNPGBE driver: > - Implement msi-x/msi interrupt configuration and management > - Create library functions for interrupt registration and cleanup > > This infrastructure enables proper interrupt handling for the > RNPGBE driver. > [...] > +/** > + * rnpgbe_set_interrupt_capability - Set MSI-X or MSI if supported > + * @mucse: pointer to private structure > + * > + * Attempt to configure the interrupts using the best available > + * capabilities of the hardware. > + * > + * @return: 0 on success, negative on failure > + **/ > +static int rnpgbe_set_interrupt_capability(struct mucse *mucse) > +{ > + int v_budget; > + > + v_budget = min_t(int, mucse->num_tx_queues, mucse->num_rx_queues); > + v_budget = min_t(int, v_budget, MAX_Q_VECTORS); these 2 lines can be simplified to min3(mucse->num_tx_queues, mucse->num_rx_queues, MAX_Q_VECTORS); > + v_budget = min_t(int, v_budget, num_online_cpus()); > + /* add one vector for mbx */> + v_budget += 1; > + v_budget = pci_alloc_irq_vectors(mucse->pdev, 1, v_budget, > + PCI_IRQ_MSI | PCI_IRQ_MSIX); > + if (v_budget < 0) > + return v_budget; > + > + if (mucse->pdev->msix_enabled) { > + /* q_vector not include mbx */ > + if (v_budget > 1) { > + mucse->flags |= M_FLAG_MSIX_EN; > + mucse->num_q_vectors = v_budget - 1; > + } else { > + mucse->flags |= M_FLAG_MSIX_SINGLE_EN; > + mucse->num_q_vectors = 1; > + } > + } else { > + /* msi use only 1 irq */ > + mucse->num_q_vectors = 1; > + mucse->flags |= M_FLAG_MSI_EN; > + } How will it work in case it's only 1 vector allocated? AFAIU, you need at least 2 irq vectors - 1 for queue processing, another one for mbx. > + > + return 0; > +}