From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S935064AbcHaOJR (ORCPT <rfc822;w@1wt.eu>);
        Wed, 31 Aug 2016 10:09:17 -0400
Received: from gloria.sntech.de ([95.129.55.99]:51152 "EHLO gloria.sntech.de"
        rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
        id S934203AbcHaOJL (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
        Wed, 31 Aug 2016 10:09:11 -0400
From: Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>, linux-kernel@vger.kernel.org,
        linux-rockchip@lists.infradead.org,
        Doug Anderson <dianders@chromium.org>,
        Brian Norris <briannorris@chromium.org>,
        Wenrui Li <wenrui.li@rock-chips.com>, Rob Herring <robh+dt@kernel.org>,
        devicetree@vger.kernel.org
Subject: Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY
Date: Wed, 31 Aug 2016 16:08:10 +0200
Message-ID: <6005500.MI6i4QbaFN@diego>
User-Agent: KMail/4.14.10 (Linux/4.6.0-1-amd64; KDE/4.14.22; x86_64; ; )
In-Reply-To: <1471661617-26432-2-git-send-email-shawn.lin@rock-chips.com>
References: <1471661617-26432-1-git-send-email-shawn.lin@rock-chips.com> <1471661617-26432-2-git-send-email-shawn.lin@rock-chips.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 7Bit
Content-Type: text/plain; charset="us-ascii"
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Hi,

Am Samstag, 20. August 2016, 10:53:37 schrieb Shawn Lin:
> This patch to add a generic PHY driver for rockchip PCIe PHY.
> Access the PHY via registers provided by GRF (general register
> files) module.
> 
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>

seems I'm late to the party, but when looking if I can apply the pcie-
devicetree patches, I found that the phy is still pending.

Apart from some error-message nitpicks below, this looks ok to me. I don't 
know enough about the actual pci phy part though.

Kishon, is this on your radar?

[...]

> +static int rockchip_pcie_phy_power_off(struct phy *phy)
> +{
> +	struct rockchip_pcie_phy *rk_phy = phy_get_drvdata(phy);
> +	int err = 0;
> +
> +	err = reset_control_assert(rk_phy->phy_rst);
> +	if (err) {
> +		pr_err("assert phy_rst err %d\n", err);

	dev_err(phy->dev, ...)

probably the same for all other pr_err invocations


> +		return err;
> +	}
> +
> +	return 0;
> +}

[...]

> +static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
> +	{
> +		.compatible = "rockchip,rk3399-pcie-phy",
> +		.data = &rk3399_pcie_data,
> +	},
> +	{}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
> +
> +static int rockchip_pcie_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct rockchip_pcie_phy *rk_phy;
> +	struct phy *generic_phy;
> +	struct phy_provider *phy_provider;
> +	struct regmap *grf;
> +	const struct of_device_id *of_id;
> +
> +	grf = syscon_node_to_regmap(dev->parent->of_node);
> +	if (IS_ERR(grf)) {
> +		dev_err(dev, "Missing rockchip,grf property\n");

		dev_err(dev, "Cannot find GRF syscon\n");


Heiko