From: Valdis.Kletnieks@vt.edu
To: Jeff Roberson <jroberson@jroberson.net>
Cc: linux-kernel@vger.kernel.org, aaronp@clustrix.com
Subject: Re: PCI-E Link training bug
Date: Tue, 03 Aug 2010 08:30:41 -0400 [thread overview]
Message-ID: <60320.1280838641@localhost> (raw)
In-Reply-To: Your message of "Tue, 03 Aug 2010 00:36:35 -1000." <alpine.BSF.2.00.1008030030430.1414@desktop>
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On Tue, 03 Aug 2010 00:36:35 -1000, Jeff Roberson said:
> At least one intel chipset will occasionally negotiate a 4x link for an 8x
> device in an 8x port. It is a known errata in the 5400 mch.
Can this get wrapped in some sort of 'if (chipset == MCH5400)'? There's no
sense in adding an entire second of delay going around this loop 4 times when
it's a valid config on a non-5400 chipset.
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next prev parent reply other threads:[~2010-08-03 12:30 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-03 10:36 PCI-E Link training bug Jeff Roberson
2010-08-03 12:30 ` Valdis.Kletnieks [this message]
2010-08-03 15:52 ` Jesse Barnes
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