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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: James Clark <james.clark@arm.com>,
	suzuki.poulose@arm.com, mathieu.poirier@linaro.org,
	coresight@lists.linaro.org
Cc: leo.yan@linaro.com, mike.leach@linaro.org,
	Leo Yan <leo.yan@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 00/15] Make ETM register accesses consistent with sysreg.h
Date: Mon, 7 Feb 2022 11:21:18 +0530	[thread overview]
Message-ID: <609d9678-e8c7-163f-86cf-0207c59db2c3@arm.com> (raw)
In-Reply-To: <20220203120604.128396-1-james.clark@arm.com>

Hi James,

On 2/3/22 5:35 PM, James Clark wrote:
> James Clark (15):
>   coresight: Make ETM4x TRCIDR0 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCIDR2 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCIDR3 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCIDR4 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCIDR5 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCCONFIGR register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCEVENTCTL1R register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCSTALLCTLR register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCVICTLR register accesses consistent with
>     sysreg.h
>   coresight: Make ETM3x ETMTECR1 register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCACATRn register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn register accesses
>     consistent with sysreg.h
>   coresight: Make ETM4x TRCSSPCICRn register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCBBCTLR register accesses consistent with
>     sysreg.h
>   coresight: Make ETM4x TRCRSCTLRn register accesses consistent with
>     sysreg.h

The changes here are very similar to each other. But they are split
into different patches according to register names just for better
review process ? OR is there any other rationale ?

- Anshuman

  parent reply	other threads:[~2022-02-07  5:56 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-03 12:05 [PATCH v2 00/15] Make ETM register accesses consistent with sysreg.h James Clark
2022-02-03 12:05 ` [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 " James Clark
2022-02-07  5:44   ` Anshuman Khandual
2022-02-07 19:02     ` Mathieu Poirier
2022-02-08 15:04     ` Suzuki K Poulose
2022-02-09  9:32       ` Mike Leach
2022-02-25 16:28         ` James Clark
2022-02-08 11:36   ` Mike Leach
2022-02-03 12:05 ` [PATCH v2 02/15] coresight: Make ETM4x TRCIDR2 " James Clark
2022-02-03 12:05 ` [PATCH v2 03/15] coresight: Make ETM4x TRCIDR3 " James Clark
2022-02-03 12:05 ` [PATCH v2 04/15] coresight: Make ETM4x TRCIDR4 " James Clark
2022-02-03 12:05 ` [PATCH v2 05/15] coresight: Make ETM4x TRCIDR5 " James Clark
2022-02-03 12:05 ` [PATCH v2 06/15] coresight: Make ETM4x TRCCONFIGR " James Clark
2022-02-03 12:05 ` [PATCH v2 07/15] coresight: Make ETM4x TRCEVENTCTL1R " James Clark
2022-02-07 19:03   ` Mathieu Poirier
2022-02-03 12:05 ` [PATCH v2 08/15] coresight: Make ETM4x TRCSTALLCTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 09/15] coresight: Make ETM4x TRCVICTLR " James Clark
2022-02-03 12:05 ` [PATCH v2 10/15] coresight: Make ETM3x ETMTECR1 " James Clark
2022-02-03 12:05 ` [PATCH v2 11/15] coresight: Make ETM4x TRCACATRn " James Clark
2022-02-03 12:06 ` [PATCH v2 12/15] coresight: Make ETM4x TRCSSCCRn and TRCSSCSRn " James Clark
2022-02-03 12:06 ` [PATCH v2 13/15] coresight: Make ETM4x TRCSSPCICRn " James Clark
2022-02-03 12:06 ` [PATCH v2 14/15] coresight: Make ETM4x TRCBBCTLR " James Clark
2022-02-03 12:06 ` [PATCH v2 15/15] coresight: Make ETM4x TRCRSCTLRn " James Clark
2022-02-08 18:58   ` Mathieu Poirier
2022-02-07  5:51 ` Anshuman Khandual [this message]
2022-02-07 10:03   ` [PATCH v2 00/15] Make ETM " James Clark

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