[PATCH v2 02/15] coresight: Make ETM4x TRCIDR2 register accesses consistent with sysreg.h

James Clark
2022-02-03T12:06:20Z

drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 +++---
drivers/hwtracing/coresight/coresight-etm4x.h | 7 +++++++
2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 107e81948f76..891cfcd93f94 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1110,11 +1110,11 @@ static void etm4_init_arch_data(void *info)
/* maximum size of resources */
etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
/* CIDSIZE, bits[9:5] Indicates the Context ID size */
- drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
+ drvdata->ctxid_size = REG_VAL(etmidr2, TRCIDR2_CIDSIZE);
/* VMIDSIZE, bits[14:10] Indicates the VMID size */
- drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
+ drvdata->vmid_size = REG_VAL(etmidr2, TRCIDR2_VMIDSIZE);
/* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
- drvdata->ccsize = BMVAL(etmidr2, 25, 28);
+ drvdata->ccsize = REG_VAL(etmidr2, TRCIDR2_CCSIZE);

etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3);
/* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 2bd8ad953b8e..a95df5686b4b 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -147,6 +147,13 @@
#define TRCIDR0_TSSIZE_SHIFT 24
#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)

+#define TRCIDR2_CIDSIZE_SHIFT 5
+#define TRCIDR2_CIDSIZE_MASK GENMASK(4, 0)
+#define TRCIDR2_VMIDSIZE_SHIFT 10
+#define TRCIDR2_VMIDSIZE_MASK GENMASK(4, 0)
+#define TRCIDR2_CCSIZE_SHIFT 25
+#define TRCIDR2_CCSIZE_MASK GENMASK(3, 0)
+