[PATCH v2 13/15] coresight: Make ETM4x TRCSSPCICRn register accesses consistent with sysreg.h

James Clark
2022-02-03T12:06:58Z

drivers/hwtracing/coresight/coresight-etm4x-sysfs.c | 2 +-
drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
index 7d9372ba1168..682819467755 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
@@ -1843,7 +1843,7 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev,

spin_lock(&drvdata->spinlock);
idx = config->ss_idx;
- config->ss_pe_cmp[idx] = val & GENMASK(7, 0);
+ config->ss_pe_cmp[idx] = val & (TRCSSPCICRn_PC_MASK << TRCSSPCICRn_PC_SHIFT);
/* must clear bit 31 in related status register on programming */
config->ss_status[idx] &= ~TRCSSCSRn_STATUS;
spin_unlock(&drvdata->spinlock);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 9c22a5b0777f..9d0978540338 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -251,6 +251,9 @@
#define TRCSSCCRn_SAC_ARC_RST_SHIFT 0
#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)

+#define TRCSSPCICRn_PC_SHIFT 0
+#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
+