Reduce IRQ latency or revise hardware?

Reduce IRQ latency or revise hardware?

[Burkhard Schölpen]

Hello,

I have a question concerning IRQ latency. In this context I mean the time from an irq being triggered by some hardware until the interrupt service routine of my driver is called, so particularly I'm not concerned about some scheduling latency. I'm dealing with some custom hardware which has got hard realtime requirements (for now). Because the standard linux kernel cannot satisfy this requirement I wonder in which direction I should go ahead:

1. Is it somehow possible to fulfill the realtime requirements of the hardware by e.g. a realtime kernel patch or some kernel configuration fine tuning (at the moment I need a maximum hardware latency of about 100 microseconds)?
2. Or is it better to work on the hardware design (it's an FPGA on a PCI-board), so it can deal with higher latencies? Is the requirement of a maximum hardware IRQ latency to high in general?

Again I would like to underline that the main task is to get the interrupt handler invoked early enough, so I can get data out of a hardware FIFO. If this FIFO produces overflows, I get into big trouble, because the following data stream will be corrupted and the hardware must be reset. The programmer of the FPGA says that the buffer size is already at the maximum.

I use an ASUS P5LD2 motherboard with a Pentium-D dualcore-processor and Debian stable (kernel 2.6.15). I would be very grateful for some hints.

Kind regards
Burkhard Schölpen
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Re: Reduce IRQ latency or revise hardware?

[Alan Cox]

On Iau, 2006-04-13 at 08:42 +0200, Burkhard Schölpen wrote:
> 1. Is it somehow possible to fulfill the realtime requirements of the
> hardware by e.g. a realtime kernel patch or some kernel configuration
> fine tuning (at the moment I need a maximum hardware latency of about
> 100 microseconds)?

I don't believe you can 100% reliably achieve 100uS on an x86 board just
because of the possible SMM, cache and tlb miss worse cases combined
with the IRQ latency of the hardware. If you have other PCI devices on
the bus then you will have real fun getting hear it.

Hand tuning all the configuration and using rtlinux as the bottom layer
might just about do it if you avoided other PCI devices that can be slow
to respond (eg ATA disk and many video cards). You'll also need a board
with no SMM mode code in use so probably ACPI disabled, and possibly
have to pick the board to suit the needs.

It may also be far easier to hit such deadlines if the chip is wired
fairly directly to one of the embedded processors so you don't have
busses in the way and you have a fast IRQ response.

> Again I would like to underline that the main task is to get the
> interrupt handler invoked early enough, so I can get data out of a
> hardware FIFO. If this FIFO produces overflows, I get into big
> trouble, because the following data stream will be corrupted and the
> hardware must be reset. The programmer of the FPGA says that the
> buffer size is already at the maximum.

The other highly latency sensitive stuff like that I've seen appears to
all bus master and have a FIFO to front that which just handles PCI
delays. That way an IRQ just means one of the bus master buffers is
full.

Alan