From: Jani Nikula <jani.nikula@linux.intel.com>
To: Yaroslav <iam@0la.ch>, "Yaroslav Bolyukin" <iam@lach.pw>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>
Cc: "Harry Wentland" <harry.wentland@amd.com>,
"Leo Li" <sunpeng.li@amd.com>,
"Rodrigo Siqueira" <siqueira@igalia.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Wayne Lin" <Wayne.Lin@amd.com>,
amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension
Date: Wed, 26 Nov 2025 16:59:09 +0200 [thread overview]
Message-ID: <61a482c23a81dc29f1fb793064c7238a98cf0143@intel.com> (raw)
In-Reply-To: <ebd974b5-88f4-4fb3-a135-bad3bf7d9b4d@0la.ch>
On Wed, 26 Nov 2025, Yaroslav <iam@0la.ch> wrote:
> On 2025-11-26 15:08, Jani Nikula wrote:
>> On Wed, 26 Nov 2025, Jani Nikula <jani.nikula@linux.intel.com> wrote:
>>> On Wed, 26 Nov 2025, Yaroslav Bolyukin <iam@lach.pw> wrote:
>>>> Current VESA vendor-specific block parsing expects real block size to be
>>>> the same as the defined struct size, use real offsets in conditionals
>>>> instead to add struct fields in future commits.
>>>>
>>>> Signed-off-by: Yaroslav Bolyukin <iam@lach.pw>
>>>
>>> I think this is something we want to backport, since MSO would break
>>> with bigger vendor-specific blocks, and that leads to black screens on
>>> MSO displays.
>>>
>>> Cc: stable@vger.kernel.org
>>> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>>
>> Oops, I'll take that back.
>>
>>>
>>>> ---
>>>> drivers/gpu/drm/drm_edid.c | 28 ++++++++++++----------------
>>>> 1 file changed, 12 insertions(+), 16 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
>>>> index 64f7a94dd9e4..a52fd6de9327 100644
>>>> --- a/drivers/gpu/drm/drm_edid.c
>>>> +++ b/drivers/gpu/drm/drm_edid.c
>>>> @@ -6544,7 +6544,7 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>> if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
>>>> return;
>>>>
>>>> - if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
>>>> + if (block->num_bytes < 5) {
>>>> drm_dbg_kms(connector->dev,
>>>> "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
>>>> connector->base.id, connector->name);
>>>> @@ -6567,24 +6567,20 @@ static void drm_parse_vesa_specific_block(struct drm_connector *connector,
>>>> break;
>>>> }
>>>>
>>>> - if (!info->mso_stream_count) {
>>>> - info->mso_pixel_overlap = 0;
>>
>> This is no longer cleared for !info->mso_stream_count.
>>
>> Perhaps the code could be reorganized to handle it better.
>
> It defaults to zero due to drm_reset_display_info()
Yes, and the code above the context initializes it from the vendor
block.
>
>>>> - return;
>>>> - }
>>>> -
>>>> - info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>> - if (info->mso_pixel_overlap > 8) {
>>>> + if (info->mso_stream_count) {
>>>> + info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
>>>> + if (info->mso_pixel_overlap > 8) {
>>>> + drm_dbg_kms(connector->dev,
>>>> + "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>> + connector->base.id, connector->name,
>>>> + info->mso_pixel_overlap);
>>>> + info->mso_pixel_overlap = 8;
>>>> + }
>>>> drm_dbg_kms(connector->dev,
>>>> - "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
>>>> + "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>> connector->base.id, connector->name,
>>>> - info->mso_pixel_overlap);
>>>> - info->mso_pixel_overlap = 8;
>>>> + info->mso_stream_count, info->mso_pixel_overlap);
>>>> }
>>>> -
>>>> - drm_dbg_kms(connector->dev,
>>>> - "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
>>>> - connector->base.id, connector->name,
>>>> - info->mso_stream_count, info->mso_pixel_overlap);
>>>> }
>>>>
>>>> static void drm_update_vesa_specific_block(struct drm_connector *connector,
>>
>
--
Jani Nikula, Intel
next prev parent reply other threads:[~2025-11-26 14:59 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-26 6:51 [PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value Yaroslav Bolyukin
2025-11-26 6:51 ` [PATCH v6 1/7] drm/edid: rename VESA block parsing functions to more generic name Yaroslav Bolyukin
2025-11-26 9:05 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 2/7] drm/edid: prepare for VESA vendor-specific data block extension Yaroslav Bolyukin
2025-11-26 9:13 ` Jani Nikula
2025-11-26 14:08 ` Jani Nikula
2025-11-26 14:50 ` Yaroslav
2025-11-26 14:59 ` Jani Nikula [this message]
2025-11-26 15:06 ` Yaroslav
2025-11-26 15:26 ` Yaroslav
2025-11-26 16:32 ` Jani Nikula
2025-11-26 14:20 ` Yaroslav
2025-11-26 14:29 ` Jani Nikula
2025-11-26 14:41 ` Yaroslav
2025-11-26 14:47 ` Jani Nikula
2025-11-26 14:53 ` Yaroslav
2025-11-26 6:51 ` [PATCH v6 3/7] drm/edid: MSO should only be used for non-eDP displays Yaroslav Bolyukin
2025-11-26 14:10 ` Jani Nikula
2025-11-26 14:22 ` Yaroslav
2025-11-26 6:51 ` [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings Yaroslav Bolyukin
2025-11-26 14:19 ` Jani Nikula
2025-11-26 14:35 ` Yaroslav
2025-11-26 14:52 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 5/7] drm/edid: for consistency, use mask everywhere for block rev parsing Yaroslav Bolyukin
2025-11-26 14:20 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 6/7] drm/edid: parse DRM VESA dsc bpp target Yaroslav Bolyukin
2025-11-26 14:25 ` Jani Nikula
2025-11-26 6:51 ` [PATCH v6 7/7] drm/amd: use fixed dsc bits-per-pixel from edid Yaroslav Bolyukin
2025-11-26 7:13 ` [PATCH v6 0/7] VESA DisplayID spec allows the device to force its DSC bits per pixel value Yaroslav
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