From: matthew.gerlach@linux.intel.com
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org,
dinguyen@kernel.org, joyce.ooi@intel.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, matthew.gerlach@altera.com,
peter.colberg@altera.com
Subject: Re: [PATCH v5 2/5] arm64: dts: agilex: add soc0 label
Date: Wed, 29 Jan 2025 11:10:25 -0800 (PST) [thread overview]
Message-ID: <622cfc1-28ea-8455-1372-4d4f76c7b613@linux.intel.com> (raw)
In-Reply-To: <c3bb46ce-d79c-4d57-93ba-90bdeb98658f@kernel.org>
On Wed, 29 Jan 2025, Krzysztof Kozlowski wrote:
> On 27/01/2025 18:35, Matthew Gerlach wrote:
>> Add a label to the soc@0 device tree node.
>>
>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>> ---
>> v3:
>> - Remove accepted patches from patch set.
>> ---
>> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>> index 1235ba5a9865..144fe74e929e 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
>> @@ -152,7 +152,7 @@ usbphy0: usbphy {
>> compatible = "usb-nop-xceiv";
>> };
>>
>> - soc@0 {
>> + soc0: soc@0 {
> This shouldn't be a separate commit, really. It serves no purpose to
> just add the label. Just like you do not add just a define in a driver
> without its user. Label like this itself is pointless. It's useful for
> something, so this should be squashed.
I will squash this label change with the user of the lable.
Thanks for the review,
Matthew Gerlach
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2025-01-29 19:10 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-27 17:35 [PATCH v5 0/5] Add PCIe Root Port support for Agilex family of chips Matthew Gerlach
2025-01-27 17:35 ` [PATCH v5 1/5] dt-bindings: PCI: altera: Add binding for Agilex Matthew Gerlach
2025-01-30 7:34 ` Krzysztof Kozlowski
2025-02-01 18:11 ` matthew.gerlach
2025-01-27 17:35 ` [PATCH v5 2/5] arm64: dts: agilex: add soc0 label Matthew Gerlach
2025-01-29 9:45 ` Krzysztof Kozlowski
2025-01-29 19:10 ` matthew.gerlach [this message]
2025-01-27 17:35 ` [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port Matthew Gerlach
2025-01-29 9:47 ` Krzysztof Kozlowski
2025-01-29 19:42 ` matthew.gerlach
2025-01-30 7:26 ` Krzysztof Kozlowski
2025-02-01 19:12 ` matthew.gerlach
2025-02-02 14:17 ` Krzysztof Kozlowski
2025-02-02 18:49 ` matthew.gerlach
2025-02-02 19:02 ` Krzysztof Kozlowski
2025-02-04 17:15 ` matthew.gerlach
2025-01-29 20:43 ` Frank Li
2025-02-01 18:07 ` matthew.gerlach
2025-01-27 17:35 ` [PATCH v5 4/5] arm64: dts: agilex: add dts enabling " Matthew Gerlach
2025-01-29 9:49 ` Krzysztof Kozlowski
2025-01-29 22:54 ` matthew.gerlach
2025-01-30 7:31 ` Krzysztof Kozlowski
2025-02-04 16:57 ` matthew.gerlach
2025-02-05 7:32 ` Krzysztof Kozlowski
2025-01-27 17:35 ` [PATCH v5 5/5] PCI: altera: Add Agilex support Matthew Gerlach
2025-01-29 9:50 ` Krzysztof Kozlowski
2025-01-29 23:03 ` matthew.gerlach
2025-02-03 14:18 ` Manivannan Sadhasivam
2025-02-03 14:42 ` Krzysztof Kozlowski
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