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(93-42-70-190.ip85.fastwebnet.it. [93.42.70.190]) by smtp.gmail.com with ESMTPSA id eh1-20020a05600c61c100b003973d425a7fsm20804729wmb.41.2022.06.21.07.46.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Jun 2022 07:46:07 -0700 (PDT) Message-ID: <62b1d9af.1c69fb81.6ff6b.7b32@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 21 Jun 2022 16:46:06 +0200 From: Christian Marangi To: Vladimir Oltean Cc: Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jonathan McDowell , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/3] net: dsa: qca8k: change only max_frame_size of mac_frame_size_reg References: <20220618062300.28541-1-ansuelsmth@gmail.com> <20220618062300.28541-2-ansuelsmth@gmail.com> <20220621123041.6y7rre26iqhhwdoa@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220621123041.6y7rre26iqhhwdoa@skbuf> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jun 21, 2022 at 03:30:41PM +0300, Vladimir Oltean wrote: > On Sat, Jun 18, 2022 at 08:22:59AM +0200, Christian Marangi wrote: > > Currently we overwrite the entire MAX_FRAME_SIZE reg instead of tweaking > > just the MAX_FRAME_SIZE value. Change this and update only the relevant > > bits. > > > > Signed-off-by: Christian Marangi > > --- > > drivers/net/dsa/qca8k.c | 8 ++++++-- > > drivers/net/dsa/qca8k.h | 3 ++- > > 2 files changed, 8 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c > > index 2727d3169c25..eaaf80f96fa9 100644 > > --- a/drivers/net/dsa/qca8k.c > > +++ b/drivers/net/dsa/qca8k.c > > @@ -2345,7 +2345,9 @@ qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) > > return 0; > > > > /* Include L2 header / FCS length */ > > - return qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + ETH_HLEN + ETH_FCS_LEN); > > + return regmap_update_bits(priv->regmap, QCA8K_MAX_FRAME_SIZE_REG, > > + QCA8K_MAX_FRAME_SIZE_MASK, > > + new_mtu + ETH_HLEN + ETH_FCS_LEN); > > } > > > > static int > > @@ -3015,7 +3017,9 @@ qca8k_setup(struct dsa_switch *ds) > > } > > > > /* Setup our port MTUs to match power on defaults */ > > - ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); > > + ret = regmap_update_bits(priv->regmap, QCA8K_MAX_FRAME_SIZE_REG, > > + QCA8K_MAX_FRAME_SIZE_MASK, > > + ETH_FRAME_LEN + ETH_FCS_LEN); > > if (ret) > > dev_warn(priv->dev, "failed setting MTU settings"); > > > > diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h > > index ec58d0e80a70..1d0c383a95e7 100644 > > --- a/drivers/net/dsa/qca8k.h > > +++ b/drivers/net/dsa/qca8k.h > > @@ -87,7 +87,8 @@ > > #define QCA8K_MDIO_MASTER_MAX_REG 32 > > #define QCA8K_GOL_MAC_ADDR0 0x60 > > #define QCA8K_GOL_MAC_ADDR1 0x64 > > -#define QCA8K_MAX_FRAME_SIZE 0x78 > > +#define QCA8K_MAX_FRAME_SIZE_REG 0x78 > > +#define QCA8K_MAX_FRAME_SIZE_MASK GENMASK(13, 0) > > What's at bits 14 and beyond? Trying to understand the impact of this change. > Most of them are reserved bits (from Documentation). The few we have Documentation of are debug bits about CRC handling, IPG and special mode where the MAC send pause frames based on the signal. It's a cleanup and seems a nice change now that we are touching this part. > > #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) > > #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) > > #define QCA8K_PORT_STATUS_SPEED_10 0 > > -- > > 2.36.1 > > -- Ansuel