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De Francesco" To: Dan Williams Cc: Davidlohr Bueso , Jonathan Cameron , Dave Jiang , Alison Schofield , Vishal Verma , Ira Weiny , Robert Richter , ming.li@zohomail.com, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: Re: [PATCH 4/4 v3] cxl/test: Simulate an x86 Low Memory Hole for tests Date: Sat, 29 Mar 2025 23:01:28 +0100 Message-ID: <6370300.Zfb76A358L@fdefranc-mobl3> In-Reply-To: <3089527.UnXabflUDm@fdefranc-mobl3> References: <20250314113708.759808-1-fabio.m.de.francesco@linux.intel.com> <67e7337f25c3a_1198729411@dwillia2-xfh.jf.intel.com.notmuch> <3089527.UnXabflUDm@fdefranc-mobl3> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart2816299.fL8zNpBrTj"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPart2816299.fL8zNpBrTj Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: "Fabio M. De Francesco" To: Dan Williams Date: Sat, 29 Mar 2025 23:01:21 +0100 Message-ID: <6370300.Zfb76A358L@fdefranc-mobl3> In-Reply-To: <3089527.UnXabflUDm@fdefranc-mobl3> MIME-Version: 1.0 On Saturday, March 29, 2025 11:16:09=E2=80=AFAM Central European Standard T= ime Fabio M. De Francesco wrote: > On Saturday, March 29, 2025 12:40:47=E2=80=AFAM Central European Standard= Time Dan Williams wrote: > > Fabio M. De Francesco wrote: > > > Simulate an x86 Low Memory Hole for the CXL tests by changing the fir= st > > > mock CFMWS range size to 768MB and the CXL Endpoint Decoder HPA range= sizes > > > to 1GB. > > >=20 > > > Since the auto-created region of cxl-test uses mock_cfmws[0], whose r= ange > > > base address is typically different from the one published by the BIO= S on > > > real hardware, the driver would fail to create and attach CXL Regions= if > > > it was run on the mock environment created by cxl-tests. > > >=20 > > > Therefore, save the mock_cfmsw[0] range base_hpa and reuse it to matc= h CXL > > > Root Decoders and Regions with Endpoint Decoders when the driver is r= un on > > > mock devices. > > >=20 > > > Since the auto-created region of cxl-test uses mock_cfmws[0], the > > > LMH path in the CXL Driver will be exercised every time the cxl-test > > > module is loaded. Executing unit test: cxl-topology.sh, confirms the > > > region created successfully with a LMH. > > >=20 > > > Cc: Alison Schofield > > > Cc: Dan Williams > > > Cc: Ira Weiny > > > Signed-off-by: Fabio M. De Francesco > > > --- > > > drivers/cxl/core/lmh.c | 35 ++++++++++++++++++++++++--= =2D- > > > drivers/cxl/core/lmh.h | 2 ++ > > > tools/testing/cxl/cxl_core_exports.c | 2 ++ > > > tools/testing/cxl/test/cxl.c | 10 ++++++++ > > > 4 files changed, 45 insertions(+), 4 deletions(-) > > >=20 > > > diff --git a/drivers/cxl/core/lmh.c b/drivers/cxl/core/lmh.c > > > index 2e32f867eb94..9c55670c1c84 100644 > > > --- a/drivers/cxl/core/lmh.c > > > +++ b/drivers/cxl/core/lmh.c > > > @@ -1,11 +1,28 @@ > > > // SPDX-License-Identifier: GPL-2.0-only > > > =20 > > > #include > > > +#include > > > + > > > #include "lmh.h" > > > =20 > > > /* Start of CFMWS range that end before x86 Low Memory Holes */ > > > #define LMH_CFMWS_RANGE_START 0x0ULL > > > =20 > > > +static u64 mock_cfmws0_range_start =3D ULLONG_MAX; > > > + > > > +void set_mock_cfmws0_range_start(const u64 start) > > > +{ > > > + mock_cfmws0_range_start =3D start; > > > +} > > > + > > > +static u64 get_cfmws_range_start(const struct device *dev) > > > +{ > > > + if (dev_is_pci(dev)) > > > + return LMH_CFMWS_RANGE_START; > > > + > > > + return mock_cfmws0_range_start; > > > +} > > > + > >=20 > > cxl_test should never result in "mock" infrastructure appearing outside > > of tools/testing/cxl/ > >=20 > > > /* > > > * Match CXL Root and Endpoint Decoders by comparing SPA and HPA ran= ges. > > > * > > > @@ -19,14 +36,19 @@ bool arch_match_spa(const struct cxl_root_decoder= *cxlrd, > > > const struct cxl_endpoint_decoder *cxled) > > > { > > > const struct range *r1, *r2; > > > + u64 cfmws_range_start; > > > int niw; > > > =20 > > > + cfmws_range_start =3D get_cfmws_range_start(&cxled->cxld.dev); > > > + if (cfmws_range_start =3D=3D ULLONG_MAX) > > > + return false; > > > + > > > r1 =3D &cxlrd->cxlsd.cxld.hpa_range; > > > r2 =3D &cxled->cxld.hpa_range; > > > niw =3D cxled->cxld.interleave_ways; > > > =20 > > > - if (r1->start =3D=3D LMH_CFMWS_RANGE_START && r1->start =3D=3D r2->= start && > > > - r1->end < (LMH_CFMWS_RANGE_START + SZ_4G) && r1->end < r2->end = && > > > + if (r1->start =3D=3D cfmws_range_start && r1->start =3D=3D r2->star= t && > > > + r1->end < (cfmws_range_start + SZ_4G) && r1->end < r2->end && > > > IS_ALIGNED(range_len(r2), niw * SZ_256M)) > > > return true; > > > =20 > > > @@ -40,9 +62,14 @@ bool arch_match_region(const struct cxl_region_par= ams *p, > > > const struct range *r =3D &cxld->hpa_range; > > > const struct resource *res =3D p->res; > > > int niw =3D cxld->interleave_ways; > > > + u64 cfmws_range_start; > > > + > > > + cfmws_range_start =3D get_cfmws_range_start(&cxld->dev); > > > + if (cfmws_range_start =3D=3D ULLONG_MAX) > > > + return false; > > > =20 > > > - if (res->start =3D=3D LMH_CFMWS_RANGE_START && res->start =3D=3D r-= >start && > > > - res->end < (LMH_CFMWS_RANGE_START + SZ_4G) && res->end < r->end= && > > > + if (res->start =3D=3D cfmws_range_start && res->start =3D=3D r->sta= rt && > > > + res->end < (cfmws_range_start + SZ_4G) && res->end < r->end && > > > IS_ALIGNED(range_len(r), niw * SZ_256M)) > > > return true; > >=20 > > Someone should be able to read the straight line CXL driver code and > > never know that an alternate implementation exists for changing these > > details. > >=20 > > So, the mock interface for this stuff should intercept at the > > arch_match_spa() and arch_match_region() level. > >=20 > > To me that looks like mark these implementations with the __mock > > attribute, similar to to_cxl_host_bridge(). Then define strong versions > > in tools/testing/cxl/mock_lmh.c. > >=20 > > The strong versions would apply memory hole semantics to both windows > > starting at zero and whatever cxl_test window you choose. > >=20 > I thought the same and wanted to use the strong/weak mechanism, but then= =20 > I noticed that the strong version (in tools/testing/cxl/mock_lmh.c) was n= ever > called. I think it never happens because of the weak version is called fr= om=20 > cxl_core. I think that all functions called from cxl_core can't be overri= de > from cxl_test.=20 >=20 > Is that deduction unfounded? Am I missing something? >=20 > Thanks, >=20 > Fabio >=20 > P.S.: Please notice that to_cxl_host_bridge() is never used in cxl_core. >=20 I mistakenly thought you were suggesting something like the wrap approach that is not possible if the caller of the wrapped function is internal to=20 the CXL core.[1] =46abio [1] https://lore.kernel.org/all/6711b7c0c0b53_3ee2294a6@dwillia2-xfh.jf.int= el.com.notmuch/ =20 --nextPart2816299.fL8zNpBrTj Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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