From: Wei Xu <xuwei5@hisilicon.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Jiancheng Xue <xuejiancheng@hisilicon.com>,
Alex Elder <elder@linaro.org>,
Peter Griffin <peter.griffin@linaro.org>,
Yang Xiwen <forbidden405@outlook.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<stable@vger.kernel.org>
Subject: Re: [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces
Date: Mon, 8 Apr 2024 16:09:29 +0800 [thread overview]
Message-ID: <6613A639.1070009@hisilicon.com> (raw)
In-Reply-To: <171256140981.12523.5652563259173425537.b4-ty@linaro.org>
Hi Krzysztof,
On 2024/4/8 15:31, Krzysztof Kozlowski wrote:
>
> On Mon, 19 Feb 2024 23:05:25 +0800, Yang Xiwen wrote:
>> The patchset fixes some warnings reported by the kernel during boot.
>>
>> The cache size info is from Processor_Datasheet_v2XX.pdf [1], Section
>> 2.2.1 Master Processor.
>>
>> The cache line size and the set-associative info are from Cortex-A53
>> Documentation [2].
>>
>> [...]
>
> It's rc3 and almost one month after last ping/talk, so apparently these got
> lost. I'll take them, but let me know if this should go via different tree.
>
>
> Applied, thanks!
Thanks!
Fine to me.
Best Regards,
Wei
>
> [1/3] arm64: dts: hi3798cv200: fix the size of GICR
> https://git.kernel.org/krzk/linux-dt/c/428a575dc9038846ad259466d5ba109858c0a023
> [2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq
> https://git.kernel.org/krzk/linux-dt/c/f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
> [3/3] arm64: dts: hi3798cv200: add cache info
> https://git.kernel.org/krzk/linux-dt/c/c7a3ad884d1dc1302dcc3295baa18917180b8bec
>
> Best regards,
>
next prev parent reply other threads:[~2024-04-08 8:09 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 15:05 [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen via B4 Relay
2024-02-19 15:05 ` [PATCH v3 1/3] arm64: dts: hi3798cv200: fix the size of GICR Yang Xiwen via B4 Relay
2024-02-19 15:05 ` [PATCH v3 2/3] arm64: dts: hi3798cv200: add GICH, GICV register space and irq Yang Xiwen via B4 Relay
2024-02-19 15:05 ` [PATCH v3 3/3] arm64: dts: hi3798cv200: add cache info Yang Xiwen via B4 Relay
2024-03-12 11:19 ` [PATCH v3 0/3] arm64: dts: hi3798cv200: fix GICR size, add cache info, maintenance irq and GICH, GICV spaces Yang Xiwen
2024-03-12 11:33 ` Wei Xu
2024-03-12 11:46 ` Yang Xiwen
2024-03-12 11:58 ` Wei Xu
2024-03-12 11:36 ` Krzysztof Kozlowski
2024-03-12 12:00 ` Wei Xu
2024-04-08 7:31 ` Krzysztof Kozlowski
2024-04-08 8:09 ` Wei Xu [this message]
2024-04-08 9:09 ` Yang Xiwen
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