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[93.34.90.105]) by smtp.gmail.com with ESMTPSA id je1-20020a05600c1f8100b00418a9961c47sm2946660wmb.47.2024.05.08.10.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 May 2024 10:17:51 -0700 (PDT) Message-ID: <663bb3bf.050a0220.38dcc.9b82@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 8 May 2024 19:17:49 +0200 From: Christian Marangi To: Conor Dooley Cc: Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/4] dt-bindings: mips: brcm: Document brcm,bmips-cbr-reg property References: <20240508170721.3023-1-ansuelsmth@gmail.com> <20240508170721.3023-3-ansuelsmth@gmail.com> <20240508-prong-serving-660e6046621d@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240508-prong-serving-660e6046621d@spud> On Wed, May 08, 2024 at 06:14:34PM +0100, Conor Dooley wrote: > On Wed, May 08, 2024 at 07:07:18PM +0200, Christian Marangi wrote: > > Document brcm,bmips-cbr-reg property. > > > > Some SoC suffer from a BUG where read_c0_brcm_cbr() might return 0 > > if called from TP1. The CBR address is always the same on the SoC > > hence it can be provided in DT to handle broken case where bootloader > > doesn't init it or SMP where read_c0_brcm_cbr() returns 0 from TP1. > > > > Usage of this property is to give an address also in these broken > > configuration/bootloader. > > > > Signed-off-by: Christian Marangi > > --- > > .../devicetree/bindings/mips/brcm/soc.yaml | 23 +++++++++++++++++++ > > 1 file changed, 23 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/mips/brcm/soc.yaml b/Documentation/devicetree/bindings/mips/brcm/soc.yaml > > index 975945ca2888..77f73ab48c11 100644 > > --- a/Documentation/devicetree/bindings/mips/brcm/soc.yaml > > +++ b/Documentation/devicetree/bindings/mips/brcm/soc.yaml > > @@ -55,6 +55,15 @@ properties: > > under the "cpus" node. > > $ref: /schemas/types.yaml#/definitions/uint32 > > > > + brcm,bmips-cbr-reg: > > + description: Reference address of the CBR. > > Pretty sure that Rob commented last time that there's no definition > anywhere here of CBR, but I don't see either a response to him or an > explanation in v3 as to what CBR means. > Sorry I missed it. > > + Some SoC suffer from a BUG where read_c0_brcm_cbr() might > > + return 0 if called from TP1. The CBR address is always the > > + same on the SoC hence it can be provided in DT to handle > > + broken case where bootloader doesn't initialise it or SMP > > + where read_c0_brcm_cbr() returns 0 from TP1. > > Why is a ?linux? function name in the binding? Surely this is just > "or in SMP systems where reading CBR returns 0 from...", no? Ditto > above. > It's really just a reference to reading c0 register at an offset, that is why I was so specific. Ok I will be more verbose. > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > patternProperties: > > "^cpu@[0-9]$": > > type: object > > @@ -64,6 +73,20 @@ properties: > > required: > > - mips-hpt-frequency > > > > +if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - brcm,bcm6358 > > + - brcm,bcm6368 > > + > > +then: > > + properties: > > + cpus: > > + required: > > + - brcm,bmips-cbr-reg > > + > > additionalProperties: true > > > > examples: > > -- > > 2.43.0 > > -- Ansuel