From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.5 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C2F1C48BE8 for ; Fri, 18 Jun 2021 12:30:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6EA9661222 for ; Fri, 18 Jun 2021 12:30:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234584AbhFRMcz (ORCPT ); Fri, 18 Jun 2021 08:32:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234425AbhFRMcD (ORCPT ); Fri, 18 Jun 2021 08:32:03 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDA9DC06121D for ; Fri, 18 Jun 2021 05:29:53 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id j18so5387540wms.3 for ; Fri, 18 Jun 2021 05:29:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=AF/9ugvcaR0qWAq1+q07h3mZXYOA6TNaXRCBlnFD4wA=; b=ETITULQfqpXRKA20QYUFH+yqebqfOtw0Q5cVBoAyLI9vux0Ej7iTJKARS+Kimvm0/V F8O9f0zTJvGG4mR64agMq7v/bRilDFvhxphA4qbIgBkg+Zt8gOw513A7pQZgi8UevDXz 6VZSYkwm8e3nc5OBGqYvxCie0SxjgsqTpBYRU219gPiaQ+kQc5K166mMSqApSJG3fbyh gUiE1AqoCEZh3i0T/C+agGwzkFo9ZkgaBhjYuz/YBntY4ao8tc5lli66OGRItw0aTq3k Ix6Fttp7si2mL0NUJzwhyB5bu01BVn4dVHPpRlAQZ+JsI65CwH02MhCaGcICU5a+bVUz uB4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=AF/9ugvcaR0qWAq1+q07h3mZXYOA6TNaXRCBlnFD4wA=; b=g06D+sCaNGkEZ8H8to01mX2j0uazgiXoqbjckFWvZAGoINdL8HSDX10+7lDNqUEXpp XQp98SfycSinZctZqlWz4sP4W2HqU+3fQwwuh/nxyu6NejYLGbthYNtGa4spM3SAKnfl zWEnvULyarSOS5Jb84qCM5YaI8EHIagV62i3e+4k9KS4qQsO5k7SnDdMjXR44TSBwNmj Jep1FXWX8SFbSBqEAp2oOmiN/f4d0Yll7i7jjS+PtBb5nDGzOmANk5Cm9dkB9fLXekcI kMnvnfH4qwAfq7tePL1TYY6G1UF3VY2Q6qmi2TNq9Q33+LuE1odhy/dO2vxybM98U6KZ LGlA== X-Gm-Message-State: AOAM531+asbelRXUdjduj4YOIDtBusLO1XnqQxKrkUbQuZ/UvJ33qnrw 802EW5M0sEsg1eyu5TuTlEdVkg== X-Google-Smtp-Source: ABdhPJy42dnPo0rChhHEcXwymBX0iZovSkFs3aYubP1cLQ9EUkEwfrWSzFijT3ic5xPBP/2udHcHCg== X-Received: by 2002:a05:600c:3ba8:: with SMTP id n40mr11371890wms.175.1624019392268; Fri, 18 Jun 2021 05:29:52 -0700 (PDT) Received: from [192.168.86.34] (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.googlemail.com with ESMTPSA id 3sm10095480wmv.6.2021.06.18.05.29.51 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 18 Jun 2021 05:29:51 -0700 (PDT) Subject: Re: [PATCH] regmap: move readable check before accessing regcache. To: Mark Brown Cc: srivasam@codeaurora.org, rafael@kernel.org, dp@opensource.wolfsonmicro.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Marek Szyprowski References: <20210618113558.10046-1-srinivas.kandagatla@linaro.org> <20210618115104.GB4920@sirena.org.uk> From: Srinivas Kandagatla Message-ID: <666da41f-173e-152d-84e5-e9b32baa60da@linaro.org> Date: Fri, 18 Jun 2021 13:29:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20210618115104.GB4920@sirena.org.uk> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks Mark for review, On 18/06/2021 12:51, Mark Brown wrote: > On Fri, Jun 18, 2021 at 12:35:58PM +0100, Srinivas Kandagatla wrote: > >> The issue that I encountered is when doing regmap_update_bits on >> a write only register. In regcache path this will not do the right >> thing as the register is not readable and driver which is using >> regmap_update_bits will never notice that it can not do a update >> bits on write only register leading to inconsistent writes and >> random hardware behavior. > > Why will use of regmap_update_bits() mean that a driver will never > notice a write failure? Shouldn't remgap_update_bits() be fixed to > report any errors it isn't reporting, or the driver fixed to check usecase is performing regmap_update_bits() on a *write-only* registers. _regmap_update_bits() checks _regmap_read() return value before bailing out. In non cache path we have this regmap_readable() check however in cached patch we do not have this check, so _regmap_read() will return success in this case so regmap_update_bits() never reports any error. driver in question does check the return value. > error codes? I really don't understand the issue you're trying to > report - what is "the right thing" and what makes you believe that a > driver can't do an _update_bits() on a write only but cached register? > Can you specify in concrete terms what the problem is. So one of recent patch ("ASoC: qcom: Fix for DMA interrupt clear reg overwriting) https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20210618&id=da0363f7bfd3c32f8d5918e40bfddb9905c86ee1 broke audio on DragonBoard 410c. This patch simply converts writes to regmap_update_bits for that particular dma channel. The register that its updating is IRQ_CLEAR register which is software "WRITE-ONLY" and Hardware read-only register. The bits in particular case is updating is a period interrupt clear bit. Because we are using regmap cache in this driver, first regmap_update_bits(map, 0x1, 0x1) on first period interrupt will update the cache and write to IRQ_CLEAR hardware register which then clears the interrupt latch. On second period interrupt we do regmap_update_bits(map, 0x1, 0x1) with the same bits, Because we are using cache for this regmap caches sees no change in the cache value vs the new value so it will never write/update IRQ_CLEAR hardware register, so hardware is stuck here waiting for IRQ_CLEAR write from driver and audio keeps repeating the last period. > >> There seems to be missing checks in regcache_read() which is >> now added by moving the orignal check in _regmap_read() before >> accessing regcache. > >> Cc: stable@vger.kernel.org >> Fixes: 5d1729e7f02f ("regmap: Incorporate the regcache core into regmap") > > Are you *sure* you've identified the actual issue here - nobody has seen I think so, my above triage does summarizes the problem in detail. > any problems with this in the past decade? Please don't just pick a > random commit for the sake of adding a Fixes tag. I did git blame and picked up this changeset which is when the cache was integrated. > >> @@ -2677,6 +2677,9 @@ static int _regmap_read(struct regmap *map, unsigned int reg, >> int ret; >> void *context = _regmap_map_get_context(map); >> >> + if (!regmap_readable(map, reg)) >> + return -EIO; >> + >> if (!map->cache_bypass) { >> ret = regcache_read(map, reg, val); >> if (ret == 0) >> @@ -2686,9 +2689,6 @@ static int _regmap_read(struct regmap *map, unsigned int reg, >> if (map->cache_only) >> return -EBUSY; >> >> - if (!regmap_readable(map, reg)) >> - return -EIO; >> - > > This puts the readability check before the cache check which will break > all drivers using the cache on write only registers. Initially I added check in regcache_read(), later I moved it to _regmap_read. do you think check in regcache_read() is the correct place? --srini >