From: nifan.cxl@gmail.com
To: Terry Bowman <Terry.Bowman@amd.com>
Cc: Dan Williams <dan.j.williams@intel.com>,
ira.weiny@intel.com, dave@stgolabs.net, dave.jiang@intel.com,
alison.schofield@intel.com, ming4.li@intel.com,
vishal.l.verma@intel.com, jim.harris@samsung.com,
ilpo.jarvinen@linux.intel.com, ardb@kernel.org,
sathyanarayanan.kuppuswamy@linux.intel.com,
linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,
Yazen.Ghannam@amd.com, Robert.Richter@amd.com,
Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org
Subject: Re: [RFC PATCH 1/9] PCI/AER: Update AER driver to call root port and downstream port UCE handlers
Date: Wed, 10 Jul 2024 13:48:31 -0700 [thread overview]
Message-ID: <668ef3a2.050a0220.96a0c.4f5c@mx.google.com> (raw)
In-Reply-To: <ecc5fbd0-52e1-443f-8e5a-2546328319b2@amd.com>
On Mon, Jun 24, 2024 at 12:56:29PM -0500, Terry Bowman wrote:
> Hi Dan,
>
> I added a response below.
>
> On 6/21/24 14:17, Dan Williams wrote:
> > Terry Bowman wrote:
> >> The AER service driver does not currently call a handler for AER
> >> uncorrectable errors (UCE) detected in root ports or downstream
> >> ports. This is not needed in most cases because common PCIe port
> >> functionality is handled by portdrv service drivers.
> >>
> >> CXL root ports include CXL specific RAS registers that need logging
> >> before starting do_recovery() in the UCE case.
> >>
> >> Update the AER service driver to call the UCE handler for root ports
> >> and downstream ports. These PCIe port devices are bound to the portdrv
> >> driver that includes a CE and UCE handler to be called.
> >>
> >> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> >> Cc: Bjorn Helgaas <bhelgaas@google.com>
> >> Cc: linux-pci@vger.kernel.org
> >> ---
> >> drivers/pci/pcie/err.c | 20 ++++++++++++++++++++
> >> 1 file changed, 20 insertions(+)
> >>
> >> diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c
> >> index 705893b5f7b0..a4db474b2be5 100644
> >> --- a/drivers/pci/pcie/err.c
> >> +++ b/drivers/pci/pcie/err.c
> >> @@ -203,6 +203,26 @@ pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
> >> pci_ers_result_t status = PCI_ERS_RESULT_CAN_RECOVER;
> >> struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
> >>
> >> + /*
> >> + * PCIe ports may include functionality beyond the standard
> >> + * extended port capabilities. This may present a need to log and
> >> + * handle errors not addressed in this driver. Examples are CXL
> >> + * root ports and CXL downstream switch ports using AER UIE to
> >> + * indicate CXL UCE RAS protocol errors.
> >> + */
> >> + if (type == PCI_EXP_TYPE_ROOT_PORT ||
> >> + type == PCI_EXP_TYPE_DOWNSTREAM) {
> >> + struct pci_driver *pdrv = dev->driver;
> >> +
> >> + if (pdrv && pdrv->err_handler &&
> >> + pdrv->err_handler->error_detected) {
> >> + const struct pci_error_handlers *err_handler;
> >> +
> >> + err_handler = pdrv->err_handler;
> >> + status = err_handler->error_detected(dev, state);
> >> + }
> >> + }
> >> +
> >
> > Would not a more appropriate place for this be pci_walk_bridge() where
> > the ->subordinate == NULL and these type-check cases are unified?
>
> It does. I can take a look at moving that.
Has that already been handled in pci_walk_bridge?
The function pci_walk_bridge() will call report_error_detected, where
the err handler will be called.
https://elixir.bootlin.com/linux/v6.10-rc6/source/drivers/pci/pcie/err.c#L80
Fan
>
> Regards,
> Terry
next prev parent reply other threads:[~2024-07-10 20:48 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-17 20:04 [RFC PATCH 0/9] Add RAS support for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports Terry Bowman
2024-06-17 20:04 ` [RFC PATCH 1/9] PCI/AER: Update AER driver to call root port and downstream port UCE handlers Terry Bowman
2024-06-20 11:21 ` Jonathan Cameron
2024-06-24 14:58 ` Terry Bowman
2024-06-21 19:17 ` Dan Williams
2024-06-24 17:56 ` Terry Bowman
2024-07-10 20:48 ` nifan.cxl [this message]
2024-07-10 21:48 ` Terry Bowman
2024-07-11 1:14 ` fan
2024-08-19 18:35 ` Fan Ni
2024-06-17 20:04 ` [RFC PATCH 2/9] PCI/AER: Call AER CE handler before clearing AER CE status register Terry Bowman
2024-06-20 11:31 ` Jonathan Cameron
2024-06-24 15:08 ` Terry Bowman
2024-06-21 19:23 ` Dan Williams
2024-06-24 18:00 ` Terry Bowman
2024-06-17 20:04 ` [RFC PATCH 3/9] PCI/portdrv: Update portdrv with an atomic notifier for reporting AER internal errors Terry Bowman
2024-06-20 12:30 ` Jonathan Cameron
2024-06-24 15:22 ` Terry Bowman
2024-06-21 19:36 ` Dan Williams
2024-06-24 18:21 ` Terry Bowman
2024-06-24 21:46 ` Dan Williams
2024-06-25 14:41 ` Terry Bowman
2024-06-26 2:54 ` Li, Ming4
2024-06-26 13:39 ` Terry Bowman
2024-06-17 20:04 ` [RFC PATCH 4/9] cxl/pci: Map CXL PCIe ports' RAS registers Terry Bowman
2024-06-20 12:46 ` Jonathan Cameron
2024-06-24 15:51 ` Terry Bowman
2024-07-02 15:18 ` Jonathan Cameron
2024-06-26 3:39 ` Li, Ming4
2024-06-17 20:04 ` [RFC PATCH 5/9] cxl/pci: Update RAS handler interfaces to support CXL PCIe ports Terry Bowman
2024-06-20 12:49 ` Jonathan Cameron
2024-07-15 17:50 ` nifan.cxl
2024-06-17 20:04 ` [RFC PATCH 6/9] cxl/pci: Add trace logging for CXL PCIe port RAS errors Terry Bowman
2024-06-20 12:53 ` Jonathan Cameron
2024-06-24 15:53 ` Terry Bowman
2024-07-02 15:53 ` Jonathan Cameron
2024-06-17 20:04 ` [RFC PATCH 7/9] cxl/pci: Add atomic notifier callback for CXL PCIe port AER internal errors Terry Bowman
2024-06-20 13:09 ` Jonathan Cameron
2024-06-24 16:09 ` Terry Bowman
2024-07-02 15:58 ` Jonathan Cameron
2024-06-26 6:22 ` Li, Ming4
2024-06-26 13:51 ` Terry Bowman
2024-06-17 20:04 ` [RFC PATCH 8/9] PCI/AER: Export pci_aer_unmask_internal_errors() Terry Bowman
2024-06-19 7:09 ` Christoph Hellwig
2024-06-19 15:40 ` Terry Bowman
2024-06-20 13:11 ` Jonathan Cameron
2024-06-24 16:22 ` Terry Bowman
2024-07-10 21:47 ` Bjorn Helgaas
2024-06-17 20:04 ` [RFC PATCH 9/9] cxl/pci: Enable interrupts for CXL PCIe ports' AER internal errors Terry Bowman
2024-06-20 13:15 ` Jonathan Cameron
2024-06-24 16:46 ` Terry Bowman
2024-07-02 16:00 ` Jonathan Cameron
2024-06-21 19:04 ` [RFC PATCH 0/9] Add RAS support for CXL root ports, CXL downstream switch ports, and CXL upstream switch ports Dan Williams
2024-06-24 17:47 ` Terry Bowman
2024-06-24 20:51 ` Dan Williams
2024-06-25 14:29 ` Terry Bowman
2024-07-25 18:49 ` fan
2024-08-19 16:21 ` Terry Bowman
2024-08-19 18:17 ` Fan Ni
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