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[87.6.196.30]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-36bbcf0cc9csm13026496f8f.17.2024.08.06.06.03.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Aug 2024 06:03:28 -0700 (PDT) Message-ID: <66b21f20.5d0a0220.200175.4b9b@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 6 Aug 2024 15:03:24 +0200 From: Christian Marangi To: Christoph Hellwig Cc: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Joern Engel , Keith Busch , Jens Axboe , Sagi Grimberg , Wolfram Sang , Florian Fainelli , Thomas Bogendoerfer , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, linux-nvme@lists.infradead.org Subject: Re: [PATCH v3 2/6] nvme: assign of_node to nvme device References: <20240806114118.17198-1-ansuelsmth@gmail.com> <20240806114118.17198-3-ansuelsmth@gmail.com> <20240806124312.GB10156@lst.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240806124312.GB10156@lst.de> On Tue, Aug 06, 2024 at 02:43:12PM +0200, Christoph Hellwig wrote: > On Tue, Aug 06, 2024 at 01:41:12PM +0200, Christian Marangi wrote: > > Introduce support for a dedicated node for a nvme card. This will be a > > subnode of the nvme controller node that will have the "nvme-card" > > compatible. > > > > This follow a similar implementation done for mmc where the specific mmc > > card have a dedicated of_node. > > > > This can be used for scenario where block2mtd module is used to declare > > partition in DT and block2mtd is called on the root block of the nvme > > card, permitting the usage of fixed-partition parser or alternative > > ones. > > Err, hell no. Why would you wire up a purely PCIe device to OF? > PCIe is self-discovering. > Well on embedded pure PCIe card most of the time are not a thing... Unless it's an enterprise product, everything is integrated in the pcb and not detachable for cost saving measure or also if the thing use PCIe protocol but it tighlty coupled with the SoC. This implementation is already very common for all kind of pcie devices like wireless card, gpio expander that are integrated in the PCB and require property in DT like calibration data, quirks or GPIO pin definitions, i2c... In modern SoC we are seeing an influx of using cheap flash storage option instead of NAND or NOR as modern hw require more space and price increase is not that high... Almost any high tier device is switching to using emmc and even attached NVME and simulating MTD with them for easy usage. Please consider this well used scenario in emebedded where PCIe is just a comunication way and the concept of detachable doesn't exist at all and things can be described in DT as static. Also these storage are used for rootfs mount so userspace is not so viable. -- Ansuel