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emacs 29.4 Date: Thu, 14 Nov 2024 07:37:20 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha512; protocol="application/pgp-signature" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On dl., de set. 23 2024, Miquel Sabat=C3=A9 Sol=C3=A0 wrote: > On dv., de set. 13 2024, Miquel Sabat=C3=A9 Sol=C3=A0 wrote: > >> Export Zicntr and Zihpm ISA extensions through the hwprobe syscall. >> >> Signed-off-by: Miquel Sabat=C3=A9 Sol=C3=A0 >> Acked-by: Jesse Taube >> Reviewed-by: Conor Dooley >> --- >> This is a resend because I sent v2 as a reply to the original thread and >> it most probably was lost by most people. Fortunately Conor picked it up >> and gave it a review. >> >> I am resending this so it can be properly applied. Thank you for your ti= me and >> sorry for the inconvenience. >> >> Changes since v1 [1]: the EXT_KEY instructions have been written in orde= r. >> >> [1] https://lore.kernel.org/linux-riscv/20240817075629.262318-1-mikisaba= te@gmail.com/ >> >> Documentation/arch/riscv/hwprobe.rst | 6 ++++++ >> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ >> arch/riscv/kernel/sys_hwprobe.c | 2 ++ >> 3 files changed, 10 insertions(+) >> >> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/r= iscv/hwprobe.rst >> index 3db60a0911df..cfd2929d0562 100644 >> --- a/Documentation/arch/riscv/hwprobe.rst >> +++ b/Documentation/arch/riscv/hwprobe.rst >> @@ -183,6 +183,9 @@ The following keys are defined: >> defined in the Atomic Compare-and-Swap (CAS) instructions manual= starting >> from commit 5059e0ca641c ("update to ratified"). >> >> + * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2= .0 >> + is supported as defined in the RISC-V ISA manual. >> + >> * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is suppor= ted as >> defined in the RISC-V Integer Conditional (Zicond) operations ex= tension >> manual starting from commit 95cf1f9 ("Add changes requested by V= ed >> @@ -192,6 +195,9 @@ The following keys are defined: >> supported as defined in the RISC-V ISA manual starting from comm= it >> d8ab5c78c207 ("Zihintpause is ratified"). >> >> + * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 >> + is supported as defined in the RISC-V ISA manual. >> + >> * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32= x is >> supported, as defined by version 1.0 of the RISC-V Vector extension= manual. >> >> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/= uapi/asm/hwprobe.h >> index b706c8e47b02..098a815b3fd4 100644 >> --- a/arch/riscv/include/uapi/asm/hwprobe.h >> +++ b/arch/riscv/include/uapi/asm/hwprobe.h >> @@ -72,6 +72,8 @@ struct riscv_hwprobe { >> #define RISCV_HWPROBE_EXT_ZCF (1ULL << 46) >> #define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 47) >> #define RISCV_HWPROBE_EXT_ZAWRS (1ULL << 48) >> +#define RISCV_HWPROBE_EXT_ZICNTR (1ULL << 49) >> +#define RISCV_HWPROBE_EXT_ZIHPM (1ULL << 50) >> #define RISCV_HWPROBE_KEY_CPUPERF_0 5 >> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) >> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) >> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwp= robe.c >> index 8d1b5c35d2a7..910b41b6a7ab 100644 >> --- a/arch/riscv/kernel/sys_hwprobe.c >> +++ b/arch/riscv/kernel/sys_hwprobe.c >> @@ -107,9 +107,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *= pair, >> EXT_KEY(ZCB); >> EXT_KEY(ZCMOP); >> EXT_KEY(ZICBOZ); >> + EXT_KEY(ZICNTR); >> EXT_KEY(ZICOND); >> EXT_KEY(ZIHINTNTL); >> EXT_KEY(ZIHINTPAUSE); >> + EXT_KEY(ZIHPM); >> EXT_KEY(ZIMOP); >> EXT_KEY(ZKND); >> EXT_KEY(ZKNE); > > Hello, > > Gently ping :) Can we get this merged for 6.12? > > Thanks! > Miquel Hello, Gently ping :) This will certainly not be included for 6.12, but is there a chance to get it for 6.13? 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