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From: Heiko =?UTF-8?B?U3TDvGJuZXI=?= <heiko@sntech.de>
To: Chukun Pan <amadeus@jmu.edu.cn>
Cc: amadeus@jmu.edu.cn, ziyao@disroot.org, devicetree@vger.kernel.org,
 linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
 linux-rockchip@lists.infradead.org
Subject: Re: [PATCH v7 4/5] arm64: dts: rockchip: add core dtsi for RK3562 SoC
Date: Sun, 11 May 2025 17:32:30 +0200
Message-ID: <6747980.G0QQBjFxQf@diego>
In-Reply-To: <20250511150101.51273-1-amadeus@jmu.edu.cn>
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Am Sonntag, 11. Mai 2025, 17:01:01 Mitteleurop=C3=A4ische Sommerzeit schrie=
b Chukun Pan:
> Hi,
>=20
> > I might be blind, but I don't see a tab missing here? #adress-cells and
> > #size-cells are in the same level of indentation as the other properties
> > of spi0? I did move the -cells down though now.
>=20
> Sorry I didn't make it clear. This refers to -cells.
>=20
> > hopefully caught all pwms now
>=20
> The pinctrl-names of pwm4 to pwm15 are still "active".
>=20
> > +		saradc0: adc@ff730000 {
> > +			compatible =3D "rockchip,rk3562-saradc";
> > +			reg =3D <0x0 0xff730000 0x0 0x100>;
> > +			interrupts =3D <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > +			#io-channel-cells =3D <1>;
>=20
> > > `#io-channel-cells` should be put above `status =3D "disabled";`
> >
> > moved now :-)
>=20
> It looks like saradc0 forgot to change.

adapted the rk3562 dtsi again, with those last remants :-)