From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7094C2D0D1 for ; Sat, 28 Dec 2019 19:01:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B74A620838 for ; Sat, 28 Dec 2019 19:01:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1577559669; bh=L7CUbGomVkDwLtlydzGJuK/FDNxPWB7mznp6Tztk/nI=; h=Date:From:To:Cc:Subject:In-Reply-To:References:List-ID:From; b=C1y+9CAnpA7KazCJTodjC0A8q31tLdiMfyLzmEsls08pFOUkrFWWkrYNzOEE0llex hnhSW9HRu/sKLkVYuP3XsnzLrCmQCaK6HNrMnJLncVs1789dmEQJ2zb9ABI8KUNUAO zGjSj2FMenz/ESuChHnKePXjTmwxGfFgOH0HsCSs= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726425AbfL1S5X (ORCPT ); Sat, 28 Dec 2019 13:57:23 -0500 Received: from disco-boy.misterjones.org ([51.254.78.96]:57470 "EHLO disco-boy.misterjones.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726310AbfL1S5X (ORCPT ); Sat, 28 Dec 2019 13:57:23 -0500 Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1ilHH5-0007NJ-2T; Sat, 28 Dec 2019 18:57:19 +0000 MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Sat, 28 Dec 2019 18:57:18 +0000 From: Marc Zyngier To: James Tai Cc: linux-realtek-soc@lists.infradead.org, mark.rutland@arm.com, devicetree@vger.kernel.org, Lorenzo Pieralisi , linux-kernel@vger.kernel.org, robh+dt@kernel.org, Robin Murphy , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/2] arm64: dts: realtek: Add RTD1319 SoC and Realtek PymParticle EVB In-Reply-To: <20191228150553.6210-3-james.tai@realtek.com> References: <20191228150553.6210-1-james.tai@realtek.com> <20191228150553.6210-3-james.tai@realtek.com> Message-ID: <6750faa33ee059ec22cf1981e7483186@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.8 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: james.tai@realtek.com, linux-realtek-soc@lists.infradead.org, mark.rutland@arm.com, devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, robin.murphy@arm.com, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2019-12-28 15:05, James Tai wrote: > Add Device Trees for Realtek RTD1319 SoC family, RTD1319 SoC and > Realtek PymParticle EVB. > > Signed-off-by: James Tai > --- > arch/arm64/boot/dts/realtek/Makefile | 2 + > .../boot/dts/realtek/rtd1319-pymparticle.dts | 43 ++++ > arch/arm64/boot/dts/realtek/rtd1319.dtsi | 12 + > arch/arm64/boot/dts/realtek/rtd13xx.dtsi | 212 ++++++++++++++++++ > 4 files changed, 269 insertions(+) > create mode 100644 arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts > create mode 100644 arch/arm64/boot/dts/realtek/rtd1319.dtsi > create mode 100644 arch/arm64/boot/dts/realtek/rtd13xx.dtsi > > diff --git a/arch/arm64/boot/dts/realtek/Makefile > b/arch/arm64/boot/dts/realtek/Makefile > index ef8d8fcbaa05..c0ae96f324eb 100644 > --- a/arch/arm64/boot/dts/realtek/Makefile > +++ b/arch/arm64/boot/dts/realtek/Makefile > @@ -9,6 +9,8 @@ dtb-$(CONFIG_ARCH_REALTEK) += rtd1295-zidoo-x9s.dtb > > dtb-$(CONFIG_ARCH_REALTEK) += rtd1296-ds418.dtb > > +dtb-$(CONFIG_ARCH_REALTEK) += rtd1319-pymparticle.dtb > + > dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-bpi-m4.dtb > dtb-$(CONFIG_ARCH_REALTEK) += rtd1395-lionskin.dtb > > diff --git a/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts > b/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts > new file mode 100644 > index 000000000000..2a36d220fef6 > --- /dev/null > +++ b/arch/arm64/boot/dts/realtek/rtd1319-pymparticle.dts > @@ -0,0 +1,43 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) > +/* > + * Copyright (c) 2019 Realtek Semiconductor Corp. > + */ > + > +/dts-v1/; > + > +#include "rtd1319.dtsi" > + > +/ { > + compatible = "realtek,pymparticle", "realtek,rtd1319"; > + model = "Realtek PymParticle EVB"; > + > + memory@2e000 { > + device_type = "memory"; > + reg = <0x2e000 0x3ffd2000>; /* boot ROM to 1 GiB or 2 GiB */ > + }; > + > + chosen { > + stdout-path = "serial0:460800n8"; > + }; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + }; > +}; > + > +/* debug console (J1) */ > +&uart0 { > + status = "okay"; > +}; > + > +/* M.2 slot (CON8) */ > +&uart1 { > + status = "disabled"; > +}; > + > +/* GPIO connector (T1) */ > +&uart2 { > + status = "disabled"; > +}; > diff --git a/arch/arm64/boot/dts/realtek/rtd1319.dtsi > b/arch/arm64/boot/dts/realtek/rtd1319.dtsi > new file mode 100644 > index 000000000000..1dcee00009cd > --- /dev/null > +++ b/arch/arm64/boot/dts/realtek/rtd1319.dtsi > @@ -0,0 +1,12 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) > +/* > + * Realtek RTD1319 SoC > + * > + * Copyright (c) 2019 Realtek Semiconductor Corp. > + */ > + > +#include "rtd13xx.dtsi" > + > +/ { > + compatible = "realtek,rtd1319"; > +}; > diff --git a/arch/arm64/boot/dts/realtek/rtd13xx.dtsi > b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi > new file mode 100644 > index 000000000000..18d063feaa7e > --- /dev/null > +++ b/arch/arm64/boot/dts/realtek/rtd13xx.dtsi > @@ -0,0 +1,212 @@ > +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) > +/* > + * Realtek RTD13xx SoC family > + * > + * Copyright (c) 2019 Realtek Semiconductor Corp. > + */ > + > +/memreserve/ 0x0000000000000000 0x000000000002e000; /* Boot ROM */ > +/memreserve/ 0x000000000002e000 0x0000000000100000; /* Boot loader */ > +/memreserve/ 0x000000000f400000 0x0000000000500000; /* Video FW */ > +/memreserve/ 0x000000000f900000 0x0000000000500000; /* Audio FW */ > +/memreserve/ 0x0000000010000000 0x0000000000014000; /* Audio FW RAM */ > + > +#include > +#include > + > +/ { > + interrupt-parent = <&gic>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + reserved-memory { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + rpc_comm: rpc@3f000 { > + reg = <0x3f000 0x1000>; > + }; > + > + rpc_ringbuf: rpc@1ffe000 { > + reg = <0x1ffe000 0x4000>; > + }; > + > + tee: tee@10100000 { > + reg = <0x10100000 0xf00000>; > + no-map; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x0>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu1: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x100>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu2: cpu@200 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x200>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + cpu3: cpu@300 { > + device_type = "cpu"; > + compatible = "arm,cortex-a55"; > + reg = <0x300>; > + enable-method = "psci"; > + next-level-cache = <&l2>; > + }; > + > + l2: l2-cache { > + compatible = "cache"; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; Nit: At some point, it'd be good to be able to describe the EL2 virtual timer interrupt too. Not specially important, but since these ARMv8.2 CPUs have it... [...] > + gic: interrupt-controller@ff100000 { > + compatible = "arm,gic-v3"; > + reg = <0xff100000 0x10000>, > + <0xff140000 0xc0000>; Are you sure about the size of the GICR region? For 4 CPUs, it should be 0x80000. Here, you have a range for 6 CPUs. Has the GIC been sized for 6 CPUs? Are you missing 2 CPUs in the DT? M. -- Jazz is not dead. It just smells funny...