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Wed, 15 Jan 2025 20:48:09 +0000 Date: Wed, 15 Jan 2025 14:48:03 -0600 From: Ira Weiny To: Alejandro Lucero Palau , Dan Williams , Ira Weiny , Dave Jiang , Fan Ni , Jonathan Cameron , Jonathan Corbet , "Andrew Morton" , Kees Cook , "Gustavo A. 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Silva" CC: Davidlohr Bueso , Alison Schofield , Vishal Verma , , , , , , Li Ming Subject: Re: [PATCH v8 02/21] cxl/mem: Read dynamic capacity configuration from the device Message-ID: <67881f03e607b_1aa45f29430@iweiny-mobl.notmuch> References: <20241210-dcd-type2-upstream-v8-0-812852504400@intel.com> <20241210-dcd-type2-upstream-v8-2-812852504400@intel.com> <67871f05cd767_20f32947f@dwillia2-xfh.jf.intel.com.notmuch> <469ac491-8733-986a-aaae-768ec28ebbec@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <469ac491-8733-986a-aaae-768ec28ebbec@amd.com> X-ClientProxiedBy: MW4P223CA0019.NAMP223.PROD.OUTLOOK.COM (2603:10b6:303:80::24) To SA1PR11MB6733.namprd11.prod.outlook.com (2603:10b6:806:25c::17) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA1PR11MB6733:EE_|CO1PR11MB4772:EE_ X-MS-Office365-Filtering-Correlation-Id: 2468995f-9d23-4c45-139c-08dd35a5eb3d X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?uZGWa4cP+sootY3JzjQF8Kf+N3UyTZYypMwZ925tEmbwOtRg5hIZPRaqD2Ft?= =?us-ascii?Q?FqTvueyRQTN5hnGZQJv6oWjvbp0LtkO+CG2ELSEoB4jEYa9gozuR0k/d8+hb?= =?us-ascii?Q?Orx4SsQfdmAnAwxADGKKGW/9Q0i9DMh+dFkypfCqBo2HTup70iMU0oy5g2Q4?= =?us-ascii?Q?Af7H/pNhMEXiqPoVN5Z2YTaAV47w5F56+T8ZiI2OgWh0Wscl7cCB+7ytmya4?= =?us-ascii?Q?Lv00DvL4/7k6L+1mjsgR6U5ukOz2t2ridzd5cnceKEh6xKAzbqWh5FicygZA?= =?us-ascii?Q?hdpzmyISyAyxr0aHQZk43+gCUWGuJwCT0UkK9/OZ4Xt3qOz9HivqhYwSm3BD?= =?us-ascii?Q?1aRPLHVx3ted53OoZkqkLJ0ahm5DfxMN5RMvuQnxWOOanuKqiLpnA6kVDDjR?= =?us-ascii?Q?SGslqB0FApP0jX2e0DoW8Rxe0hIPDr7ZLi/bmgucE/BdNNtHKLLLw5EZvNZW?= =?us-ascii?Q?R2O0xzahVfhVT0A8zTn2tkC6fkRLkc/F5vtjVFZ65gQdzvUWvhgh1jpDgAHd?= =?us-ascii?Q?7YDw51UFtA/oU50mXNzUH8P4kyVqP+fjiT/Ww0Ps1OrHq8jjOoJnc0Juqqw7?= =?us-ascii?Q?0K7d/tQ9JTv9k7iPWxmq915BXOINzN1Ugz/PHlXh7ZbShCiDzI7MeExNiOvd?= =?us-ascii?Q?E5zNXhlGahnfQavJDSUvv50jpsinTWN1CeKX3luU1WHeUbgkvQDGf9jmbof+?= =?us-ascii?Q?z6fv22UcJIGBDjNNPOyG9XKcKmEM/yOnQvSqyXPzB80DdyoW59tLykbopEnV?= =?us-ascii?Q?LF5VluK/WiMxm6tsF2kcJrUrEI08qs6OOCIdPkQ8YQIU2I3FCsIAErdGpNG1?= =?us-ascii?Q?11ul66aKCmWvQhmaNrkgLjPFrI37dZc+sILf/3cLYcSTPM3lKYl5K33D/TJa?= =?us-ascii?Q?tmytm2Kb/XJO+wlVW/pY6j5z2+BY7Hh2OtCtU3GJoTfQEKjkSjRfuy1gRGxB?= =?us-ascii?Q?0nauhQx9digaClCpyvkwHXuOSF46lPIMy3tD6TfOfOUtF9Lzft/GxBPhDq6n?= =?us-ascii?Q?FwPu2wN9hIpZevW5R11yPTPsFz2VbUuZirlTWwHoqvKH4wH7HcJaWX3vpABZ?= =?us-ascii?Q?4CnxUq5ESAGpvmeVlqLUoD/3G3Q8xFMxdrzXlXx+OIuQTyT6ubAsR11yuvMk?= =?us-ascii?Q?cqiXYRY0L5ff/EqgnNgWwdlTCwE8sVVuuzWyp1DbDQGXrWfCrrgaxzzWwFOe?= =?us-ascii?Q?u/4rar5c5GjRWcX1k87MMhaO/0x60D3bE+NWyLjcYRpSgKYesTwn4azKhA63?= =?us-ascii?Q?x6bSw/8cPTE0REXHINAAHybuS2JFI2DfpmhywNd9JSEoL7lnlCcNKJaw7jvB?= =?us-ascii?Q?TVIpuOmJ9sric05cWHlVDSlwVJHzbEy455dRJ1wtwxRPACLAa2Zh3CeCaMqO?= =?us-ascii?Q?w+vTkFjnL0MZTSjYLuUtFIoQHYvyoElMyylTF6YHPVUNFk8a1o3nFZFZ9+Tf?= =?us-ascii?Q?yH2S5CrOPSRJnU52aQWTBazh32EixNsHeBDMdr0gTmkH3NFgntQE6FoXPmka?= =?us-ascii?Q?GX6Is5wu2Ot5qhcTx5/nisjsnRsI/HJ6gb3EUdwE7qOxvaJyX7Rd5j8jh+Oi?= =?us-ascii?Q?rufqDA9YI20VOlFuY9sMVvqhXbvjg7U/fnXfqJ1S?= X-MS-Exchange-CrossTenant-Network-Message-Id: 2468995f-9d23-4c45-139c-08dd35a5eb3d X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6733.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2025 20:48:09.0650 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6L5UYah6ZV+TdezyJdMQh4vQ7gkSRGp+8Oe1/F6ROMVgIIla+m54Nb5QaEbnMsaDWLAyLh5IkWlyaqVe51hE0Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO1PR11MB4772 X-OriginatorOrg: intel.com Alejandro Lucero Palau wrote: > > On 1/15/25 02:35, Dan Williams wrote: > > Ira Weiny wrote: [snip] > >> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > >> index e8907c403edbd83c8a36b8d013c6bc3391207ee6..05a0718aea73b3b2a02c608bae198eac7c462523 100644 > >> --- a/drivers/cxl/cxlmem.h > >> +++ b/drivers/cxl/cxlmem.h > >> @@ -403,6 +403,7 @@ enum cxl_devtype { > >> CXL_DEVTYPE_CLASSMEM, > >> }; > >> > >> +#define CXL_MAX_DC_REGION 8 > > Please no, lets not sign up to have the "which cxl 'region' concept are > > you referring to?" debate in perpetuity. "DPA partition", "DPA > > resource", "DPA capacity" anything but "region". > > > > > > This next comment is not my main point to discuss in this email > (resources initialization is), but I seize it for giving my view in this > one. > > Dan, you say later we (Linux) are not obligated to use "questionable > naming decisions of specifications", but we should not confuse people > either. > > Maybe CXL_MAX_DC_HW_REGION would help here, for differentiating it from > the kernel software cxl region construct. I think we will need a CXL > kernel dictionary sooner or later ... I agree. I have had folks confused between spec and code and I'm really trying to differentiate hardware region vs software partition. > > >> /** > >> * struct cxl_dpa_perf - DPA performance property entry > >> * @dpa_range: range for DPA address > >> @@ -434,6 +435,8 @@ struct cxl_dpa_perf { > >> * @dpa_res: Overall DPA resource tree for the device > >> * @pmem_res: Active Persistent memory capacity configuration > >> * @ram_res: Active Volatile memory capacity configuration > >> + * @dc_res: Active Dynamic Capacity memory configuration for each possible > >> + * region > >> * @serial: PCIe Device Serial Number > >> * @type: Generic Memory Class device or Vendor Specific Memory device > >> * @cxl_mbox: CXL mailbox context > >> @@ -449,11 +452,23 @@ struct cxl_dev_state { > >> struct resource dpa_res; > >> struct resource pmem_res; > >> struct resource ram_res; > >> + struct resource dc_res[CXL_MAX_DC_REGION]; > > This is throwing off cargo-cult alarms. The named pmem_res and ram_res > > served us well up until the point where DPA partitions grew past 2 types > > at well defined locations. I like the array of resources idea, but that > > begs the question why not put all partition information into an array? > > > > This would also head off complications later on in this series where the > > DPA capacity reservation and allocation flows have "dc" sidecars bolted > > on rather than general semantics like "allocating from partition index N > > means that all partitions indices less than N need to be skipped and > > marked reserved". > > > I guess this is likely how you want to change the type2 resource > initialization issue and where I'm afraid these two patchsets are going > to collide at. > > If that is the case, both are going to miss the next kernel cycle since > it means major changes, but let's discuss it without further delays for > the sake of implementing the accepted changes as soon as possible, and I > guess with a close sync between Ira and I. > > BTW, in the case of the Type2, there are more things to discuss which I > do there. I'm looking at your set again because I think I missed this detail. After looking into this more I think a singular array of resources could be done without to much major surgery. The question for type 2 is what interface does the core export for accelerators to request these resources? Or do we export a function like add_dpa_res() and let drivers do that directly? Dan is concerned about storing duplicate information about the partitions. For DCD I think it should call add_dpa_res() to create resources on the fly as I detect partition information from the device. For type 2 they can call that however/whenever they want. We can even make this an xarray for complete flexibility with how many partitions a device can have. Although I'm not sure if the spec allows for that on type 2. Does it? Ira [snip]