Re: [PATCH v7 03/17] CXL/PCI: Introduce PCIe helper functions pcie_is_cxl() and pcie_is_cxl_port()

Dan Williams
2025-02-12T19:52:01Z

Bowman, Terry wrote:
[..]
> >
> > Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Ok, I will add the comment.
>
> Would you like for me to add the enable/disable internal error logic to cxl_port_probe()? I can but want to confirm.

If it's quick, go ahead. Otherwise I think it is ok to leave it in
aer_probe() for now if only because this is not the only place in the
CXL stack that needs to be fixed up to honor the fact that DVSEC 3 and 7
are only reliable post link-up.

I.e. the other places I know of are:

- cxl_acpi: fails to probe for cachemem component registers on
disconnected root ports

- cxl_switch_port_probe(): enumerates all dports even though not all may
be link up yet

So, in the interest of moving this set forward, that wider fix can be
deferred to a later rework series that address all the dynamic DVSEC 3,7
issues.