Re: [PATCH] KVM: arm64: Add missing ERX*_EL1 registers

[James Morse <james.morse@arm.com>]

Hi Oliver,

On 15/01/2024 14:47, Oliver Upton wrote:
> On Wed, Jan 10, 2024 at 12:20:30PM +0000, Marc Zyngier wrote:
>> If my reading of the ARM ARM is correct, these registers only exist if
>> FEAT_RASv1p1 is implemented. Which means that we shouldn't handle
>> those as RAZ/WI unconditionally, but instead check for what we
>> advertise to the guest and handle it accordingly.
> 
> Can we go a step further and just stop advertising RAS to guests? I don't
> expect VMs to gain much from our RAZ/WI implementation.

These CPU registers would describe the error in a kernel-first setup, but firmware-first
has its own in-memory way of doing that.

The CPU features indicates the IESB feature and ESB-instruction exist to fence errors, and
that the CPU uses the ESR_ELx.{S,A}ET bits to describe the CPU state after an error. These
are all useful as part of the notification of an error, be that kernel-first or
firmware-first.

When its supported by the hardware, the VMM can inject an asynchronous external abort
using KVM_GET_VCPU_EVENTS - otherwise the ESR_ELx.ISS bits are all imp-def, meaning all
errors are catastrophic.

Doing this would skip save/restore of VDISR_EL2, is there any other reason to do it?


> Conditional
> RAZ/WI would still be helpful in this case for migrated VMs that have
> 'seen' the feature.


Thanks,

James