Re: [PATCH v7 12/17] cxl/pci: Add error handler for CXL PCIe Port RAS errors

Ira Weiny
2025-03-05T00:22:36Z

Terry Bowman wrote:
> Introduce correctable and uncorrectable (UCE) CXL PCIe Port Protocol Error
> handlers.
>
> The handlers will be called with a 'struct pci_dev' parameter
> indicating the CXL Port device requiring handling. The CXL PCIe Port
> device's underlying 'struct device' will match the port device in the
> CXL topology.
>
> Use the PCIe Port's device object to find the matching CXL Upstream Switch
> Port, CXL Downstream Switch Port, or CXL Root Port in the CXL topology. The
> matching CXL Port device should contain a cached reference to the RAS
> register block. The cached RAS block will be used in handling the error.
>
> Invoke the existing __cxl_handle_ras() or __cxl_handle_cor_ras() using
> a reference to the RAS registers as a parameter. These functions will use
> the RAS register reference to indicate an error and clear the device's RAS
> status.
>
> Update __cxl_handle_ras() to return PCI_ERS_RESULT_PANIC in the case
> an error is present in the RAS status. Otherwise, return
> PCI_ERS_RESULT_NONE.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>

[snip]

> +
> +static void cxl_port_cor_error_detected(struct pci_dev *pdev)

This causes a build error in this patch because it is defined but not used
until later.

Might be worth deferring to the future patch?

Ira