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(93-34-90-129.ip49.fastwebnet.it. [93.34.90.129]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d1fd6b2acsm29215905e9.0.2025.03.14.14.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Mar 2025 14:19:32 -0700 (PDT) Message-ID: <67d49d64.050a0220.35694d.b7ab@mx.google.com> X-Google-Original-Message-ID: Date: Fri, 14 Mar 2025 22:19:29 +0100 From: Christian Marangi To: "Russell King (Oracle)" Cc: Andrew Lunn , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vladimir Oltean , Srinivas Kandagatla , Heiner Kallweit , Maxime Chevallier , Matthias Brugger , AngeloGioacchino Del Regno , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v12 07/13] net: mdio: regmap: add support for multiple valid addr References: <20250309172717.9067-1-ansuelsmth@gmail.com> <20250309172717.9067-8-ansuelsmth@gmail.com> <67cdd3c9.df0a0220.1c827e.b244@mx.google.com> <0c6cb801-5592-4449-b776-a337161b3326@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Mar 14, 2025 at 09:01:56PM +0000, Russell King (Oracle) wrote: > On Fri, Mar 14, 2025 at 08:41:33PM +0100, Andrew Lunn wrote: > > On Sun, Mar 09, 2025 at 06:45:43PM +0100, Christian Marangi wrote: > > > On Sun, Mar 09, 2025 at 05:36:49PM +0000, Russell King (Oracle) wrote: > > > > On Sun, Mar 09, 2025 at 06:26:52PM +0100, Christian Marangi wrote: > > > > > +/* If a non empty valid_addr_mask is passed, PHY address and > > > > > + * read/write register are encoded in the regmap register > > > > > + * by placing the register in the first 16 bits and the PHY address > > > > > + * right after. > > > > > + */ > > > > > +#define MDIO_REGMAP_PHY_ADDR GENMASK(20, 16) > > > > > +#define MDIO_REGMAP_PHY_REG GENMASK(15, 0) > > > > > > > > Clause 45 PHYs have 5 bits of PHY address, then 5 bits of mmd address, > > > > and then 16 bits of register address - significant in that order. Can > > > > we adjust the mask for the PHY address later to add the MMD between > > > > the PHY address and register number? > > > > > > > > > > Honestly to future proof this, I think a good idea might be to add > > > helper to encode these info and use Clause 45 format even for C22. > > > Maybe we can use an extra bit to signal if the format is C22 or C45. > > > > > > BIT(26) 0: C22 1:C45 > > > GENMASK(25, 21) PHY ADDR > > > GENMASK(20, 16) MMD ADDR > > > GENMASK(15, 0) REG > > > > If you look back at older kernels, there was some helpers to do > > something like this, but the C22/C45 was in bit 31. When i cleaned up > > MDIO drivers to have separate C22 and C45 read/write functions, they > > become redundant and they were removed. You might want to bring them > > back again. > > I'd prefer we didn't bring that abomination back. The detail about how > things are stored in regmap should be internal within regmap, and I > think it would be better to have an API presented that takes sensible > parameters, rather than something that's been encoded. > Well problem is that regmap_write and regmap_read will take max 2 value at the very end (reg and value) so it's really a matter of making the encoding part internal but encoding it can't be skipped. You are suggesting to introduce additional API like mdio_regmap_write(regmap, phy, addr, val); mdio_mmd_regmap_write(regmap, phy, mmd, addr, val); And the encoding is done internally? My concern is the decoding part from the .write/read_bits regmap OPs. I guess for that also some helper should be exposed (to keep the decoding/encoding internal to the driver and not expose the _abomination_) What do you think? -- Ansuel