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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
To: Mark Brown <broonie@kernel.org>
Cc: "AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Dong Aisheng" <aisheng.dong@nxp.com>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"Yassine Oudjana" <y.oudjana@protonmail.com>,
	"Laura Nao" <laura.nao@collabora.com>,
	"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
	"Chia-I Wu" <olvaffe@gmail.com>,
	"Chen-Yu Tsai" <wenst@chromium.org>,
	kernel@collabora.com, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc
Date: Tue, 27 Jan 2026 19:18:02 +0100	[thread overview]
Message-ID: <6800096.lOV4Wx5bFT@workhorse> (raw)
In-Reply-To: <4ea31b0d-af6e-44f7-86e4-35a43b8c71e7@sirena.org.uk>

On Tuesday, 27 January 2026 18:25:04 Central European Standard Time Mark Brown wrote:
> On Tue, Jan 27, 2026 at 05:01:35PM +0000, Mark Brown wrote:
> > On Fri, Oct 10, 2025 at 10:47:09PM +0200, Nicolas Frattaroli wrote:
> > > When CLK_OPS_PARENT_ENABLE was introduced, it guarded various clock
> > > operations, such as setting the rate or switching parents. However,
> > > another operation that can and often does touch actual hardware state is
> > > recalc_rate, which may also be affected by such a dependency.
> > 
> > I'm seeing boot regressions in -next on the Avenger96 which bisect to
> > this patch in -next.  The board resets during startup:
> 
> I am also seeing some similar regressions even earlier on i.MX8MP
> platforms, though they're resetting even earlier before any output is
> produced (even with earlycon).  Didn't confirm yet with a revert or
> anything though.
> 

Someone else seemingly bisected to this commit on i.MX8MP as well
and replied to the RESEND of the series, and confirmed with a
revert[1].

I'm somewhat surprised by this, because to me it doesn't make intuitive
sense that some platforms would rely on CLK_OPS_PARENT_ENABLE to not
enable the parent clock during a recalc.

Can someone let me know which clocks (with which parent) in those
affected devices is causing this? I'm wondering if this change
unmasked some undeclared dependency that it's now stumbling over
because it's enabling the parent earlier than ever.

Would appreciate if we could fix up the affected platforms rather
than revert this, because the platform I added this for was
definitely using a parent-child relationship, and definitely
needed to have the parent clock on during recalc.

I can always bring back the RPM model I went for previously, but
that feels like more of a hack around this caveat than a proper
description of the clock relationship.

To not have me break everyone's -next for days on end, feel free
to drop this patch. MT8196, which this was added for, doesn't boot
with mainline yet anyway.

Kind regards,
Nicolas Frattaroli

https://lore.kernel.org/all/6239343.lOV4Wx5bFT@steina-w/ [1]





  reply	other threads:[~2026-01-27 18:18 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-10 20:47 [PATCH v3 0/5] MediaTek PLL Refactors and Fixes Nicolas Frattaroli
2025-10-10 20:47 ` [PATCH v3 1/5] clk: Respect CLK_OPS_PARENT_ENABLE during recalc Nicolas Frattaroli
2025-10-16 20:52   ` Brian Masney
2025-10-17 12:21     ` Nicolas Frattaroli
2025-10-20 19:36       ` Brian Masney
2026-01-27 17:01   ` Mark Brown
2026-01-27 17:25     ` Mark Brown
2026-01-27 18:18       ` Nicolas Frattaroli [this message]
2026-01-27 23:14         ` Mark Brown
2026-01-28 14:09           ` Nicolas Frattaroli
2026-01-28 14:47             ` Mark Brown
2026-01-28 14:55               ` Alexander Stein
2026-01-28 15:21                 ` Mark Brown
2026-01-28 16:31                   ` Nicolas Frattaroli
2026-01-28 17:08                     ` Mark Brown
2026-01-28 16:04               ` Nicolas Frattaroli
2026-01-28 19:01                 ` Stephen Boyd
2026-01-28 19:59                   ` Nicolas Frattaroli
2026-02-02 16:54                   ` Mark Brown
2025-10-10 20:47 ` [PATCH v3 2/5] clk: mediatek: Refactor pll registration to pass device Nicolas Frattaroli
2025-10-10 20:47 ` [PATCH v3 3/5] clk: mediatek: Pass device to clk_hw_register for PLLs Nicolas Frattaroli
2025-10-10 20:47 ` [PATCH v3 4/5] clk: mediatek: Refactor pllfh registration to pass device Nicolas Frattaroli
2025-10-10 20:47 ` [PATCH v3 5/5] clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks Nicolas Frattaroli

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