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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDA4NCBTYWx0ZWRfX7Obh15bhfig0 4wUJ3eThgHs1PwuBWTOafE612CJ1WnD1qwlNNhXFnGMDV8BTxHAasGZrZwWCuhG8NdpQbNOSgk9 DWDq6ymGuFEyLj7Vt25qIfsDDCgRsw8= X-Authority-Analysis: v=2.4 cv=DYgnbPtW c=1 sm=1 tr=0 ts=6a50b0e9 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=TLRsrNMnCJaxhW4YLJwA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-ORIG-GUID: IrErQXzQn4FbKZ9xMWZjsjmh-UvzeCYB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDA4NCBTYWx0ZWRfX3PI8Zwy1jDNN nlq+k4/QLI/g9DxIN8wHtnkj/lnBe1g6BIfWwQTgnmmd9Ewco/Rk1Akq1ZDXvDpHFU3CpHuRjo9 JWJFXwKtzlsuiZPacvfrFZDkhPyI5ONKjvrT8TYlarFSsswPD9v/7yT4SIhAzuSnVNAdD9++OkB OnWEzZG5hdn6kGJt/8wrqbwIlbaZDDsfqqGi0oyVew/0AdDVDpsX4AshzBMqoTuxORe+Kj9xnYA A2HSR1TMgqueRt9HeGBBIwSSoX1RS4yse/qI1JNvxbHxXHjMuv2A0xVXNdHU4frljRQo53MgvBy KaclzUKXxLyG/oE9xqbMQyYcB1GoduFEkSxqsF7Y77z63CVSWVnhwXURPL2nrVebMVDvtfVu/XF rm0H1KGkvLQbXNbE8wErwA6vscFDBsVhouSJVqrW1jOK0+pe8IWzcwFKzDrAj9TUTlRQE6RfSMB Ohe3F5Anfr5eaFABlzw== X-Proofpoint-GUID: IrErQXzQn4FbKZ9xMWZjsjmh-UvzeCYB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_02,2026-07-09_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100084 On 7/10/26 4:19 AM, Qiang Yu wrote: > On Mon, Jun 29, 2026 at 11:20:07AM +0200, Konrad Dybcio wrote: >> On 6/29/26 7:05 AM, Qiang Yu wrote: >>> On Wed, Jun 17, 2026 at 01:19:49PM +0200, Konrad Dybcio wrote: >>>> On 5/19/26 7:47 AM, Qiang Yu wrote: >>>>> Glymur PCIe3 uses a single shared Gen5x8 QMP PHY block. Model PCIe3a and >>>>> PCIe3b as consumers of that shared PHY provider instead of separate PHY >>>>> nodes. >>>>> >>>>> Update the DTS wiring to: >>>>> - point GCC PCIe3A/3B pipe parents to the shared PHY clock outputs >>>>> - add PCIe3a controller node and route PCIe3a/PCIe3b port phys to >>>>> &pcie3_phy using two-cell PHY arguments >>>>> - configure the shared PHY node with link-mode and dual pipe outputs >>>>> >>>>> Use QMP_PCIE_GLYMUR_MODE_* dt-binding macros for mode selection. >>>>> >>>>> Signed-off-by: Qiang Yu >>>>> --- >>>> >>>> [...] >>>> >>>>> + pcie3a: pci@1c10000 { >>>>> + device_type = "pci"; >>>>> + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; >>>>> + reg = <0x0 0x01c10000 0x0 0x3000>, >>>>> + <0x0 0x70000000 0x0 0xf20>, >>>>> + <0x0 0x70000f40 0x0 0xa8>, >>>>> + <0x0 0x70001000 0x0 0x4000>, >>>>> + <0x0 0x70100000 0x0 0x100000>, >>>>> + <0x0 0x01c13000 0x0 0x1000>; >>>>> + reg-names = "parf", >>>>> + "dbi", >>>>> + "elbi", >>>>> + "atu", >>>>> + "config", >>>>> + "mhi"; >>>>> + #address-cells = <3>; >>>>> + #size-cells = <2>; >>>>> + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, >>>>> + <0x02000000 0x0 0x70000000 0x0 0x70300000 0x0 0x3d00000>, >>>>> + <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, >>>>> + <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; >>>>> + >>>>> + bus-range = <0 0xff>; >>>>> + >>>>> + dma-coherent; >>>>> + >>>>> + linux,pci-domain = <3>; >>>>> + num-lanes = <8>; >>>> >>>> Is it fine to keep num-lanes 8 here even for configurations with >>>> bifurcated PHY? >>>> >>>> I would assume so, given essentially this is a x8 host, whose 4 >>>> lanes may simply be effectively NC >>>> >>> Actually, on existing platforms, the PCIe3a and PCIe3b controllers are >>> never enabled at the same time. When PCIe3a is exposed, it is always in an >>> x8 slot. But if we have a x4+x4 platform in future, we can simply override >>> num-lanes to 4 in the board.dts. >> >> My question is whether that will be necessary - if yes, sure, we >> can do it, but if not, we can conclude on this early and not have >> to fight over it in a couple months >> > I think we do need to override it in that case. If both PCIe3a and PCIe3b > are enabled in x4+x4 mode but PCIe3a keeps num-lanes = <8>, userspace > will see an 8-lane slot. If an x8-capable EP is connected to that slot, > both ends will advertise x8 support, but the link is up at x4. That looks > like a genuine bug from the user's point of view. Do we know what's advertised on x86 PCs with bifurcated lanes? Konrad