From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BACC8240243 for ; Tue, 14 Jan 2025 01:30:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736818249; cv=none; b=o9py627i6h/5VCtGZiMgA1WWPIEYFqvAXmhv0nHqz5ywvKpetsoqb2YLdRXMvl5FtzkHHMJivgoT1OAeUcZnag9Vmi+pUBBcFAldESmulyYEHzbH9MPgLeqrHUHhtuXZWC/TUaSP/aWDEFD74MAYV74CmKhQn7swEN29fRFA/z0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736818249; c=relaxed/simple; bh=l7cP/7niqCYyJ+3zOE+Rn2U13FaxkV8mRP1zm2IZhfU=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=ESFMB9B2M3rg/JfCvAwvxdjzNXYrmvnUYMW/U6TIRJbcmYzU/Ku22m0Y9i3INut5dBlU7etnBvH2YlknRXXV+SE5qSXWYrRbzIAW0QJSQ3H0TGwe5reNso2rDwj6AbTpuVt8eY6El2vMSvGqRVu1aAIzkJLu7lU2sgSZr3+vrXo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tXVjl-000000003mF-0N49; Mon, 13 Jan 2025 20:28:57 -0500 Message-ID: <6856727624fe88dd4cca3343f6fe8d2919939a2d.camel@surriel.com> Subject: Re: [PATCH v4 11/12] x86/mm: enable AMD translation cache extensions From: Rik van Riel To: Andrew Cooper Cc: akpm@linux-foundation.org, bp@alien8.de, dave.hansen@linux.intel.com, jannh@google.com, kernel-team@meta.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, nadav.amit@gmail.com, peterz@infradead.org, thomas.lendacky@amd.com, x86@kernel.org, zhengqi.arch@bytedance.com Date: Mon, 13 Jan 2025 20:28:57 -0500 In-Reply-To: <09807556-46fe-46ae-ae3f-7083a1b12253@citrix.com> References: <20250112155453.1104139-12-riel@surriel.com> <09807556-46fe-46ae-ae3f-7083a1b12253@citrix.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.1 (3.54.1-1.fc41) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Sender: riel@surriel.com On Mon, 2025-01-13 at 11:32 +0000, Andrew Cooper wrote: > > +++ > > b/arch/x86/kernel/cpu/amd.c @@ -1071,6 +1071,9 @@ static void > > init_amd(struct cpuinfo_x86 *c)=C2=A0=20 > > =C2=A0 /* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE > > MSR writes. */ > > =C2=A0 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); > > + + if (cpu_feature_enabled(X86_FEATURE_INVLPGB)) + > > msr_set_bit(MSR_EFER, _EFER_TCE);=C2=A0 } > > =C2=A0 > > =C2=A0#ifdef CONFIG_X86_32 >=20 > I don't think this is wise.=C2=A0 TCE is orthogonal to INVLPGB. >=20 > Either Linux is safe with TCE turned on, and it should be turned on > everywhere (it goes back to Fam10h CPUs IIRC), or Linux isn't safe > with > TCE turned on, and this needs to depend on some other condition. >=20 > Or, is this a typo and did you mean to check the TCE CPUID bit, > rather > than the INVLPGB CPUID bit? You're right, this should just check against X86_FEATURE_TCE, which I did not realize was a separate feature bit. I've changed this for the next version of the series. Thank you! --=20 All Rights Reversed.