Re: [PATCH v11 2/4] dt-bindings: remoteproc: add Tightly Coupled Memory (TCM) bindings

Tanmay Shah
2024-02-29T23:45:32Z

Thanks for reviews.

Ack to all comments, I will address in next revision.

Tanmay

On 2/29/24 3:59 AM, Krzysztof Kozlowski wrote:
> On 19/02/2024 18:44, Tanmay Shah wrote:
> > From: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> >
> > Introduce bindings for TCM memory address space on AMD-xilinx Zynq
> > UltraScale+ platform. It will help in defining TCM in device-tree
> > and make it's access platform agnostic and data-driven.
> >
> > Tightly-coupled memories(TCMs) are low-latency memory that provides
> > predictable instruction execution and predictable data load/store
> > timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory
> > banks on the ATCM and BTCM ports, for a total of 128 KB of memory.
> >
> > The TCM resources(reg, reg-names and power-domain) are documented for
> > each TCM in the R5 node. The reg and reg-names are made as required
> > properties as we don't want to hardcode TCM addresses for future
> > platforms and for zu+ legacy implementation will ensure that the
> > old dts w/o reg/reg-names works and stable ABI is maintained.
> >
> > It also extends the examples for TCM split and lockstep modes.
> >
> > Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
> > Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
> > ---
> >
> > Changes in v11:
> > - Fix yamllint warning and reduce indentation as needed
> >
> > .../remoteproc/xlnx,zynqmp-r5fss.yaml | 192 ++++++++++++++++--
> > 1 file changed, 170 insertions(+), 22 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
> > index 78aac69f1060..77030edf41fa 100644
> > --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
> > +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
> > @@ -20,9 +20,21 @@ properties:
> > compatible:
> > const: xlnx,zynqmp-r5fss
> >
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 2
> > +
> > + ranges:
> > + description: |
> > + Standard ranges definition providing address translations for
> > + local R5F TCM address spaces to bus addresses.
> > +
> > xlnx,cluster-mode:
> > $ref: /schemas/types.yaml#/definitions/uint32
> > enum: [0, 1, 2]
> > + default: 1
> > description: |
> > The RPU MPCore can operate in split mode (Dual-processor performance), Safety
> > lock-step mode(Both RPU cores execute the same code in lock-step,
> > @@ -37,7 +49,7 @@ properties:
> > 2: single cpu mode
> >
> > patternProperties:
> > - "^r5f-[a-f0-9]+$":
> > + "^r5f@[0-9a-f]+$":
> > type: object
> > description: |
> > The RPU is located in the Low Power Domain of the Processor Subsystem.
> > @@ -54,9 +66,6 @@ patternProperties:
> > compatible:
> > const: xlnx,zynqmp-r5f
> >
> > - power-domains:
> > - maxItems: 1
>
> Why power-domains are being dropped? This should have widest constraints
> if you later customize it.
>
> > -
> > mboxes:
> > minItems: 1
> > items:
> > @@ -101,35 +110,174 @@ patternProperties:
> >
> > required:
> > - compatible
> > - - power-domains
>
> Don't drop power domains.
>
>
> >
> > - unevaluatedProperties: false
> > +allOf:
>
> allOf block goes after required:
>
> > + - if:
> > + properties:
> > + xlnx,cluster-mode:
> > + enum:
> > + - 1
> > + then:
> > + patternProperties:
> > + "^r5f@[0-9a-f]+$":
> > + type: object
> > +
> > + properties:
> > + reg:
>
> reg is missing in your patternProperties earlier.
>
>
>
> Best regards,
> Krzysztof
>