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[93.34.88.81]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47a88923ce6sm397615e9.18.2025.12.10.09.17.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Dec 2025 09:17:06 -0800 (PST) Message-ID: <6939ab12.050a0220.29891a.9a37@mx.google.com> X-Google-Original-Message-ID: Date: Wed, 10 Dec 2025 18:17:01 +0100 From: Christian Marangi To: Bjorn Helgaas Cc: Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH 1/1] PCI: Use resource_set_range() that correctly sets ->end References: <20251208145654.5294-1-ilpo.jarvinen@linux.intel.com> <20251210171319.GA3530931@bhelgaas> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20251210171319.GA3530931@bhelgaas> On Wed, Dec 10, 2025 at 11:13:19AM -0600, Bjorn Helgaas wrote: > On Mon, Dec 08, 2025 at 04:56:54PM +0200, Ilpo Järvinen wrote: > > __pci_read_base() sets resource start and end addresses when resource > > is larger than 4G but pci_bus_addr_t or resource_size_t are not capable > > of representing 64-bit PCI addresses. This creates a problematic > > resource that has non-zero flags but the start and end addresses do not > > yield to resource size of 0 but 1. > > > > Replace custom resource addresses setup with resource_set_range() > > that correctly sets end address as -1 which results in resource_size() > > returning 0. > > > > For consistency, also use resource_set_range() in the other branch that > > does size based resource setup. > > IIUC this fixes an ath11k regression (and probably others). And > typically when booting a 32-bit kernel with a device with a BAR larger > than 4GB? > > Christian, is there any dmesg snippet we could include here to help > users diagnose the problem? I guess the "can't handle BAR larger than > 4GB" message is probably one clue. > > Are you able to test this and verify that it fixes the regression you > saw? > No my regression was on a different section and for AHB cards, no PCI. (I sent a fix for my regression on the net mailing list) Could be hard to find a device with 4+ gb of ram that is not x86 or on an ipq SoC. > > Fixes: 23b13bc76f35 ("PCI: Fail safely if we can't handle BARs larger than 4GB") > > Link: https://lore.kernel.org/all/20251207215359.28895-1-ansuelsmth@gmail.com/T/#m990492684913c5a158ff0e5fc90697d8ad95351b > > Signed-off-by: Ilpo Järvinen > > Cc: stable@vger.kernel.org > > Cc: Christian Marangi > > --- > > drivers/pci/probe.c | 6 ++---- > > 1 file changed, 2 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > > index 124d2d309c58..b8294a2f11f9 100644 > > --- a/drivers/pci/probe.c > > +++ b/drivers/pci/probe.c > > @@ -287,8 +287,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, > > if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) > > && sz64 > 0x100000000ULL) { > > res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; > > - res->start = 0; > > - res->end = 0; > > + resource_set_range(res, 0, 0); > > pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", > > res_name, (unsigned long long)sz64); > > goto out; > > @@ -297,8 +296,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, > > if ((sizeof(pci_bus_addr_t) < 8) && l) { > > /* Above 32-bit boundary; try to reallocate */ > > res->flags |= IORESOURCE_UNSET; > > - res->start = 0; > > - res->end = sz64 - 1; > > + resource_set_range(res, 0, sz64); > > pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", > > res_name, (unsigned long long)l64); > > goto out; > > > > base-commit: 43dfc13ca972988e620a6edb72956981b75ab6b0 > > -- > > 2.39.5 > > -- Ansuel