Re: [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2

[John Garry <john.g.garry@oracle.com>]

On 05/01/2023 21:13, Ian Rogers wrote:
>>> This may be a feasible idea. The value of slots comes from the register PMMIR_EL1, which I can read in
>>> /sys/bus/event_source/device/armv8_pmuv3_*/caps/slots. But how do I replace the slots in MetricExpr with the
>>> read slots values? Currently I understand that parameters in metricExpr only support events and constants.
>>>
>> Maybe during runtime we could create a pseudo metric/event for SLOT.
> For Intel we do this by just having a different constant for each
> architecture. It is fairly easy to add a new "literal", so you could
> add a #slots in expr__get_literal:
> https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git/tree/tools/perf/util/expr.c?h=perf*core*n407__;LyM!!ACWV5N9M2RV99hQ!IHcZFuFaLdQDQvVOnHVlbbME2S4aW8GohWUkydlejpi7ifFz61r7RutGXReRt0d88X_vDfkTySCiuD2PqOA$  
> Populating it would be the challenge 😄

Thanks for the pointer. I think that the challenge in populating it 
really comes down to whether we would really want to make this generic.

I suppose that for arm64 we could have a method which accesses this 
PMMIR_EL1 register, while for other archs we could have a weak function 
which just returns NAN. If other archs want to use this key expr, they 
can add their own method.

Out of curiosity, do you know if x86 has such a capability to get this 
slot info from HW?

Thanks,
John