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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>,
	markgross@kernel.org,
	Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	platform-driver-x86@vger.kernel.org,
	LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] platform/x86: ISST: Use fuse enabled mask instead of allowed levels
Date: Fri, 29 Sep 2023 15:14:47 +0300 (EEST)	[thread overview]
Message-ID: <6991c0fa-7b3c-b99a-4ac4-9c499d4d808b@linux.intel.com> (raw)
In-Reply-To: <20230925194555.966743-2-srinivas.pandruvada@linux.intel.com>

On Mon, 25 Sep 2023, Srinivas Pandruvada wrote:

> Allowed level mask is a mask of levels, which are currently allowed
> to dynamically switch. But even dynamic switching is not allowed,

even if ?

> user should be able to check all parameters for selection via BIOS.

I think you're lacking a negation in the above paragraph because it sounds 
like there's an internal contradiction in it. Can you please take a look.

-- 
 i.


> So when passing the level mask for display to user space, use fuse
> enabled mask, which has all levels.
> 
> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
> ---
>  drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> index 37f17e229419..48465636aadb 100644
> --- a/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> +++ b/drivers/platform/x86/intel/speed_select_if/isst_tpmi_core.c
> @@ -712,7 +712,7 @@ static int isst_if_get_perf_level(void __user *argp)
>  		return -EINVAL;
>  
>  	perf_level.max_level = power_domain_info->max_level;
> -	perf_level.level_mask = power_domain_info->pp_header.allowed_level_mask;
> +	perf_level.level_mask = power_domain_info->pp_header.level_en_mask;
>  	perf_level.feature_rev = power_domain_info->pp_header.feature_rev;
>  	_read_pp_info("current_level", perf_level.current_level, SST_PP_STATUS_OFFSET,
>  		      SST_PP_LEVEL_START, SST_PP_LEVEL_WIDTH, SST_MUL_FACTOR_NONE)
> 

  reply	other threads:[~2023-09-29 12:14 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-25 19:45 [PATCH 0/3] Minor SST optimizations Srinivas Pandruvada
2023-09-25 19:45 ` [PATCH 1/3] platform/x86: ISST: Use fuse enabled mask instead of allowed levels Srinivas Pandruvada
2023-09-29 12:14   ` Ilpo Järvinen [this message]
2023-09-30 12:48     ` srinivas pandruvada
2023-09-25 19:45 ` [PATCH 2/3] platform/x86: ISST: Allow level 0 to be not present Srinivas Pandruvada
2023-09-29 12:16   ` Ilpo Järvinen
2023-09-25 19:45 ` [PATCH 3/3] platform/x86: intel_speed_select_if: Remove hardcoded map size Srinivas Pandruvada
2023-09-26 13:16   ` Andy Shevchenko
2023-09-26 15:04     ` srinivas pandruvada
2023-09-26 15:23       ` Andy Shevchenko

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