From: Krzysztof Kozlowski <krzk@kernel.org>
To: Manikandan Karunakaran Pillai <mpillai@cadence.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"kw@linux.com" <kw@linux.com>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>
Cc: "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations
Date: Thu, 27 Mar 2025 15:15:19 +0100 [thread overview]
Message-ID: <6a487a73-3f2d-4373-8e02-ba749181bdfb@kernel.org> (raw)
In-Reply-To: <CH2PPF4D26F8E1C1CBD2A866C59AA55CD7AA2A12@CH2PPF4D26F8E1C.namprd07.prod.outlook.com>
On 27/03/2025 12:19, Manikandan Karunakaran Pillai wrote:
> Document the compatible property for the newly added values for PCIe EP and
> RP configurations. Fix the compilation issues that came up for the existing
> Cadence bindings
These are two different commits.
>
> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
> ---
> .../bindings/pci/cdns,cdns-pcie-ep.yaml | 12 +-
> .../bindings/pci/cdns,cdns-pcie-host.yaml | 119 +++++++++++++++---
> 2 files changed, 110 insertions(+), 21 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> index 98651ab22103..aa4ad69a9b71 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.yaml
> @@ -7,14 +7,22 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence PCIe EP Controller
>
> maintainers:
> - - Tom Joseph <tjoseph@cadence.com>
> + - Manikandan K Pillai <mpillai@cadence.com>
>
> allOf:
> - $ref: cdns-pcie-ep.yaml#
>
> properties:
> compatible:
> - const: cdns,cdns-pcie-ep
> + oneOf:
> + - const: cdns,cdns-pcie-ep
> + - const: cdns,cdns-pcie-hpa-ep
What is hpa? Which soc is that?
I don't think this should keep growing, but instead use SoC based
compatibles.
Anyway, that's enum.
> + - const: cdns,cdns-cix-pcie-hpa-ep
What is cix? If you want to stuff here soc in the middle, then no, no
no. Please read devicetree spec and writing bindings how the compatibles
are created.
> + - description: PCIe EP controller from cadence
> + items:
> + - const: cdns,cdns-pcie-ep
> + - const: cdns,cdns-pcie-hpa-ep
> + - const: cdns,cdns-cix-pcie-hpa-ep
This makes no sense.
>
> reg:
> maxItems: 2
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> index a8190d9b100f..bb7ffb9ddaf9 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
> @@ -7,16 +7,30 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
> title: Cadence PCIe host controller
>
> maintainers:
> - - Tom Joseph <tjoseph@cadence.com>
> + - Manikandan K Pillai <mpillai@cadence.com>
>
> allOf:
> - - $ref: cdns-pcie-host.yaml#
> + - $ref: cdns-pcie.yaml#
Why?
>
> properties:
> + "#size-cells":
> + const: 2
> + "#address-cells":
> + const: 3
Huh? Why? Nothing here makes sense.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-03-27 14:15 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20250327105429.2947013-1-mpillai@cadence.com>
2025-03-27 10:59 ` [PATCH 0/7] Enhance the PCIe controller driver Manikandan Karunakaran Pillai
[not found] ` <20250327111106.2947888-1-mpillai@cadence.com>
2025-03-27 11:19 ` [PATCH 1/7] dt-bindings: pci: cadence: Extend compatible for new platform configurations Manikandan Karunakaran Pillai
2025-03-27 14:15 ` Krzysztof Kozlowski [this message]
2025-03-28 5:07 ` Manikandan Karunakaran Pillai
2025-03-28 7:20 ` Krzysztof Kozlowski
2025-03-28 8:22 ` Krzysztof Kozlowski
2025-03-28 8:48 ` Hans Zhang
2025-03-28 9:17 ` Krzysztof Kozlowski
2025-03-30 14:59 ` Hans Zhang
[not found] ` <20250327111127.2947944-1-mpillai@cadence.com>
2025-03-27 11:26 ` [PATCH 2/7] PCI: cadence: Add header support for PCIe next generation controllers Manikandan Karunakaran Pillai
2025-03-27 12:01 ` Hans Zhang
2025-04-09 20:39 ` Bjorn Helgaas
2025-04-11 4:16 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111200.2948071-1-mpillai@cadence.com>
2025-03-27 11:40 ` [PATCH 4/7] PCI: cadence: Add support for PCIe Endpoint HPA controllers Manikandan Karunakaran Pillai
2025-04-09 22:15 ` Bjorn Helgaas
2025-04-11 4:23 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111241.2948184-1-mpillai@cadence.com>
2025-03-27 11:42 ` [PATCH 6/7] PCI: cadence: Add callback functions for Root Port and EP controller Manikandan Karunakaran Pillai
2025-04-09 22:45 ` Bjorn Helgaas
2025-04-11 4:26 ` Manikandan Karunakaran Pillai
[not found] ` <20250327111256.2948250-1-mpillai@cadence.com>
2025-03-27 11:43 ` [PATCH 7/7] PCI: cadence: Update support for TI J721e boards Manikandan Karunakaran Pillai
2025-03-27 12:03 ` [PATCH 0/7] Enhance the PCIe controller driver Hans Zhang
2025-03-27 14:16 ` Krzysztof Kozlowski
2025-03-27 14:43 ` Manikandan Karunakaran Pillai
2025-03-27 14:46 ` Krzysztof Kozlowski
2025-04-09 17:08 ` manivannan.sadhasivam
2025-04-11 4:08 ` Manikandan Karunakaran Pillai
2025-04-09 20:11 ` Bjorn Helgaas
2025-04-11 4:10 ` Manikandan Karunakaran Pillai
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