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From: Christian Marangi <ansuelsmth@gmail.com>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Bjorn Helgaas" <helgaas@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Ryder Lee" <ryder.lee@mediatek.com>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@collabora.com>,
	"Jianjun Wang" <jianjun.wang@mediatek.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v5 2/2] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581
Date: Sat, 15 Aug 2026 13:04:45 +0200	[thread overview]
Message-ID: <6a8047d1.3527643f.2d620e.3236@mx.google.com> (raw)
In-Reply-To: <5qulrgfnwzuo556hxsyg3iweqv6i57ll3chhhb3nxe7lgr6fff@4l3s5rotnpab>

On Sat, Aug 15, 2026 at 08:16:56AM +0200, Manivannan Sadhasivam wrote:
> On Thu, Aug 13, 2026 at 09:30:54PM +0200, Christian Marangi wrote:
> > On Thu, Aug 13, 2026 at 12:08:20PM -0500, Bjorn Helgaas wrote:
> > > On Thu, Aug 06, 2026 at 06:53:32PM +0200, Christian Marangi wrote:
> > > > The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes
> > > > mode (x2 link) by bonding it with the second PCIe lane (PCIe1). This is
> > > > done by configuring the PCIe MUX in the SCU register.
> > > > 
> > > > To correctly configure PCIe0 in x2 link, define in DT the following
> > > > additional properties:
> > > > 
> > > >   - additional reg, 'sec-pcie-mac' for the secondary PCIe.
> > > >   - PERSTOUT reset for both main and secondary PCIE0, called 'perstout' and
> > > >     'sec-perstout'
> > > >   - 'airoha,scu' property to correctly configure the SCU register for the
> > > >     PCIe MUX
> > > >   - 'num-lanes' set to '2' to enable PCIe0 in x2 link
> > > > 
> > > > In such configuration the EQ preset are configured to the same values.
> > > > 
> > > > To permit correct configuration of the PCIe link, additional logic is added
> > > > to assert and deassert the PERSTOUT resets. Support of these additional
> > > > reset was introduced in Airoha clk driver with commit
> > > > 6712f48eb3a1 ("clk: en7523: add support for dedicated PCIe PERSTOUT reset")
> > > > and on backporting of this commit also the clk driver change will be
> > > > needed.
> > > 
> > > I don't see 6712f48eb3a1 in upstream or linux-next.  Is this SHA1
> > > going to valid if we merge this for v7.3?
> > 
> > I picked that sha1 from the git pull for the staging clk tree.
> > 
> 
> Ah, I missed it. In this case the SHA should be dropped and maybe we can refer
> the lore link of the patch?
> 

Just yesterday it was picked and it's present in clk-next [1].

The commit didn't change as merge commit are used so the sha1 is valid.

I think we can keep it?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/drivers/clk/clk-en7523.c?h=clk-next&id=6712f48eb3a15842925171441505fa2e7699c57e

-- 
	Ansuel

  reply	other threads:[~2026-08-15 11:04 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-06 16:53 [PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock Christian Marangi
2026-08-06 16:53 ` [PATCH v5 1/2] dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes Christian Marangi
2026-08-06 16:53 ` [PATCH v5 2/2] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 Christian Marangi
2026-08-13 17:08   ` Bjorn Helgaas
2026-08-13 19:30     ` Christian Marangi
2026-08-15  6:16       ` Manivannan Sadhasivam
2026-08-15 11:04         ` Christian Marangi [this message]
2026-08-07  3:24 ` [PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock Chen-Yu Tsai
2026-08-07 15:20   ` Bjorn Helgaas
     [not found]     ` <CA+_ehUxQfWRRec4q2ZvC12nYAeV2VGm1xCFrTWeN6sEL+qkXBw@mail.gmail.com>
2026-08-09 14:08       ` Benjamin Larsson
2026-08-09 14:14         ` Christian Marangi (Ansuel)
2026-08-09 15:27           ` Benjamin Larsson
2026-08-10 10:33     ` Chen-Yu Tsai
2026-08-10 10:55       ` Christian Marangi (Ansuel)
2026-08-11 19:43         ` Benjamin Larsson
2026-08-12  7:59         ` Chen-Yu Tsai
2026-08-13  5:21 ` Manivannan Sadhasivam
2026-08-14 22:36 ` Bjorn Helgaas

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