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Thu, 19 Jan 2023 16:16:16 GMT Received: from smtprelay05.fra02v.mail.ibm.com ([9.218.2.225]) by ppma06ams.nl.ibm.com (PPS) with ESMTPS id 3n3knfpwm7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 19 Jan 2023 16:16:16 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay05.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 30JGGDKh43188556 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 19 Jan 2023 16:16:13 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 527FE2004D; Thu, 19 Jan 2023 16:16:13 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3CAF920040; Thu, 19 Jan 2023 16:16:12 +0000 (GMT) Received: from [9.171.48.94] (unknown [9.171.48.94]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 19 Jan 2023 16:16:12 +0000 (GMT) Message-ID: <6cb75bd724f45bca8371235fd51132e987fb0f8a.camel@linux.ibm.com> Subject: Re: [PATCH v4 5/7] iommu/dma: Allow a single FQ in addition to per-CPU FQs From: Niklas Schnelle To: Joerg Roedel , Will Deacon , Robin Murphy , Jason Gunthorpe , Wenjia Zhang Cc: Matthew Rosato , Gerd Bayer , Pierre Morel , iommu@lists.linux.dev, linux-s390@vger.kernel.org, borntraeger@linux.ibm.com, hca@linux.ibm.com, gor@linux.ibm.com, gerald.schaefer@linux.ibm.com, agordeev@linux.ibm.com, svens@linux.ibm.com, linux-kernel@vger.kernel.org, Julian Ruess Date: Thu, 19 Jan 2023 17:16:11 +0100 In-Reply-To: <5692d7fbc3d4bd2ac624c82a77f642c36a2cf04e.camel@linux.ibm.com> References: <20230104120543.308933-1-schnelle@linux.ibm.com> <20230104120543.308933-6-schnelle@linux.ibm.com> <5692d7fbc3d4bd2ac624c82a77f642c36a2cf04e.camel@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.46.3 (3.46.3-1.fc37) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 1VXH6vcfoXBdYwEcG0mshrkGkEKk-jTY X-Proofpoint-GUID: 1VXH6vcfoXBdYwEcG0mshrkGkEKk-jTY Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.122.1 definitions=2023-01-19_09,2023-01-19_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 adultscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 suspectscore=0 spamscore=0 mlxlogscore=475 phishscore=0 lowpriorityscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2301190130 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2023-01-19 at 16:55 +0100, Niklas Schnelle wrote: > On Wed, 2023-01-04 at 13:05 +0100, Niklas Schnelle wrote: > > In some virtualized environments, including s390 paged memory guests, > > IOTLB flushes are used to update IOMMU shadow tables. Due to this, they > > are much more expensive than in typical bare metal environments or > > non-paged s390 guests. In addition they may parallelize more poorly in > > virtualized environments. This changes the trade off for flushing IOVAs > > such that minimizing the number of IOTLB flushes trumps any benefit of > > cheaper queuing operations or increased paralellism. > >=20 > > In this scenario per-CPU flush queues pose several problems. Firstly > > per-CPU memory is often quite limited prohibiting larger queues. > > Secondly collecting IOVAs per-CPU but flushing via a global timeout > > reduces the number of IOVAs flushed for each timeout especially on s390 > > where PCI interrupts may not be bound to a specific CPU. > >=20 > > Thus let's introduce a single flush queue mode IOMMU_DOMAIN_DMA_SQ that > > reuses the same queue logic but only allocates a single global queue > > allowing larger batches of IOVAs to be freed at once and with larger > > timeouts. This is to allow the common IOVA flushing code to more closely > > resemble the global flush behavior used on s390's previous internal DMA > > API implementation. > >=20 > > As we now support two different variants of flush queues rename the > > existing __IOMMU_DOMAIN_DMA_FQ to __IOMMU_DOMAIN_DMA_LAZY to indicate > > the general case of having a flush queue and introduce separate > > __IOMMU_DOMAIN_DMA_PERCPU_Q and __IOMMU_DOMAIN_DMA_SINGLE_Q bits to > > indicate the two queue variants. > >=20 > > Link: https://lore.kernel.org/linux-iommu/3e402947-61f9-b7e8-1414-fde00= 6257b6f@arm.com/ > > Signed-off-by: Niklas Schnelle > > --- > > v2 -> v3: > > - Rename __IOMMU_DOMAIN_DMA_FQ to __IOMMU_DOMAIN_DMA_LAZY to make it mo= re clear > > that this bit indicates flush queue use independent of the exact queu= ing > > strategy >=20 ---8<--- >=20 > >=20=20 > > - for (i =3D 0; i < IOVA_FQ_SIZE; i++) > > - INIT_LIST_HEAD(&fq->entries[i].freelist); > > + if (rc) { > > + pr_warn("iova flush queue initialization failed\n"); > > + return rc; > > } > >=20 > ---8<---=20 > >=20 > > mutex_unlock(&group->mutex); > > @@ -2896,10 +2900,10 @@ static int iommu_change_dev_def_domain(struct i= ommu_group *group, > > } > >=20=20 > > /* We can bring up a flush queue without tearing down the domain */ > > - if (type =3D=3D IOMMU_DOMAIN_DMA_FQ && prev_dom->type =3D=3D IOMMU_DO= MAIN_DMA) { > > + if (!!(type & __IOMMU_DOMAIN_DMA_LAZY) && prev_dom->type =3D=3D IOMMU= _DOMAIN_DMA) { > > ret =3D iommu_dma_init_fq(prev_dom); > > if (!ret) > > - prev_dom->type =3D IOMMU_DOMAIN_DMA_FQ; > > + prev_dom->type =3D type; >=20 > Here domain->type is set only after calling iommu_dma_init_fq(). Actually I think even in the current code the above and the similar code in iommu.c isn't ideal. When going from DMA to DMA-FQ with a bound driver the flush queue is used from the moment that WRITE_ONCE(cookie- >fq_domain, domain) executes in iommu_dma_init_fq() so there is a window where the flush queue is already used but domain->type is still DMA. By adding a type parameter to iommu_dma_init_fq() we can set domain->type before the WRITE_ONCE() and thus close this window and it even makes the callsites of iommu_dma_init_fq() simpler. >=20 > > goto out; > > } > >=20=20 >=20