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From: Justin Lai <justinlai0215@realtek.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "kuba@kernel.org" <kuba@kernel.org>,
	"davem@davemloft.net" <davem@davemloft.net>,
	"edumazet@google.com" <edumazet@google.com>,
	"pabeni@redhat.com" <pabeni@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>
Subject: RE: [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code
Date: Mon, 21 Aug 2023 05:31:09 +0000	[thread overview]
Message-ID: <6d35d56f78b7452b9330c3257748fa3c@realtek.com> (raw)
In-Reply-To: <4b630aeb-3098-4108-b8dc-7da6e55a7cf1@lunn.ch>

> > > Is the 'line' speed of the MAC fixed? It operates at one speed, and that is
> it?
> >
> > Hi, Andrew
> >
> 
> > The "line" speed of the MAC is fixed 5G, but the throughput will be
> > determined according to the speed of the PCIe link. For example, if
> > the link speed is gen 3, the throughput will be 5G. if the link speed
> > is gen 2, the throughput will be 2.5G. if the link speed is gen 1, the
> > throughput will be 1G.
> 
> ksettings does not return throughput, it returns the line speed. throughput is
> determined by a lot of different things, can the CPU handle frames fast enough,
> is the memory bandwidth high enough, what is happening on other ports of
> the PCIe switch etc.
> 
> There is at least one driver i know of which reports a warning at probe time, if
> it finds the device is on a bus which cannot support the full bandwidth. Maybe
> copy that.
> 

Hi, Andrew

Thanks for your guidance, we have represented the actual connection speed in the next version.

> > There is no extra fields in DMA descriptors for tagging protocol. The
> > tag added by switch hardware instead of this driver.
> 
> > > Are the I2C, MDIO and SPI bus masters also hanging off a PCIE
> > > endpoint? Can they probe independently? I'm just want to check this
> > > should not be part of an MFD driver.
> >
> 
> > The I2C, MDIO and SPI bus masters are not hanging off the PCIE
> > endpoints, but on the switch core.
> 
> So the switch core is also an PCIE endpoint?

Sorry, please allow me to explain again.
The RTL90xx Series supports I2C, MDC/MDIO and SPI slave to access the registers of Ethernet Switch Core and the external CPU could manage it via these pins.
You are right, there is a tag protocol in the switch core. But It's for the other ports, usually the cpu port, not this pcie gmac interface.
You can think of this pcie gmac as a NIC connecting to the external ethernet switch directly.

> 
>    Andrew
> .

  reply	other threads:[~2023-08-21  5:32 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-15 14:37 [PATCH net-next v3 0/2] Add Realtek automotive PCIe driver Justin Lai
2023-08-15 14:37 ` [PATCH net-next v3 1/2] net/ethernet/realtek: Add Realtek automotive PCIe driver code Justin Lai
2023-08-15 15:33   ` Andrew Lunn
2023-08-17  7:32     ` Justin Lai
2023-08-17 12:22       ` Andrew Lunn
2023-08-18 11:56         ` Justin Lai
2023-08-18 12:16           ` Andrew Lunn
2023-08-21  5:31             ` Justin Lai [this message]
2023-08-21 13:12               ` Andrew Lunn
2023-08-21 15:07                 ` Justin Lai
2023-08-21 17:21                   ` Andrew Lunn
2023-08-22  3:26                     ` Justin Lai
2023-08-17 15:53   ` Jakub Kicinski
2023-08-18  6:44     ` Justin Lai
2023-08-15 14:37 ` [PATCH net-next v3 2/2] MAINTAINERS: Add the rtase ethernet driver entry Justin Lai

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