From: Krzysztof Kozlowski <krzk@kernel.org>
To: Sudeep Holla <sudeep.holla@arm.com>,
Alim Akhtar <alim.akhtar@samsung.com>
Cc: 'Devang Tailor' <dev.tailor@samsung.com>,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
faraz.ata@samsung.com
Subject: Re: [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920
Date: Wed, 5 Feb 2025 16:52:07 +0100 [thread overview]
Message-ID: <6d4d93a5-9a03-4cc3-9ef4-ab64562560f3@kernel.org> (raw)
In-Reply-To: <Z5zPpz6WAbPJX701@bogus>
On 31/01/2025 14:27, Sudeep Holla wrote:
>>>
>> [snip]
>> > + l3_cache_cl0: l3-cache0 {
>> You can add one node for cl0 and cl1, say "l3_cache_cl0_cl1" and
>> Remove the specific node for CL1, because both are same.
>>
>
> What do you mean by "both are same" ?
> Do you mean both have exact same properties but are physically different
> caches ? OR
> Do you mean it is just one shared cache ?
>
> If former, we still need distinct node to get the cacheinfo about
> shareability correct. If this is about avoiding duplication of errors,
> you can probably define some macro and avoid it, but we need 2 nodes in
> the devicetree.
>
> If latter, you suggestion is correct.
No answers here, so I drop this patch from my queue.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-02-05 15:52 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250108054224epcas5p399f3d734f8d9f82e5ae75d183d1a5344@epcas5p3.samsung.com>
2025-01-08 5:50 ` [PATCH v2] arm64: dts: add cpu cache information to ExynosAuto-v920 Devang Tailor
2025-01-31 11:49 ` Alim Akhtar
2025-01-31 13:27 ` Sudeep Holla
2025-02-05 15:52 ` Krzysztof Kozlowski [this message]
2025-02-05 16:10 ` Alim Akhtar
2025-02-17 8:45 ` Devang Tailor
2025-02-05 16:07 ` Alim Akhtar
2025-02-17 10:36 ` Krzysztof Kozlowski
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