public inbox for linux-kernel@vger.kernel.org
 help / color / mirror / Atom feed
From: Andi Kleen <andi@firstfloor.org>
To: linux-kernel@vger.kernel.org, x86@kernel.org, hpa@zytor.com
Cc: Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 12/17] x86: MCE: Enable MCE_INTEL for 32bit new MCE
Date: Wed, 27 May 2009 01:18:11 +0200	[thread overview]
Message-ID: <6dfa191bd595ff969fafb3603ba464254ca895a7.1243377662.git.ak@linux.intel.com> (raw)
In-Reply-To: <2bc54830cc9e63d090dc461db0bdf99fc3d3cd4a.1243377662.git.ak@linux.intel.com>
In-Reply-To: <bce28247059ad80b138de8ae9f22f9d13c856589.1243377662.git.ak@linux.intel.com>

From: Andi Kleen <ak@linux.intel.com>

Enable the 64bit MCE_INTEL code (CMCI, thermal interrupts) for 32bit NEW_MCE.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 arch/x86/Kconfig                       |    2 +-
 arch/x86/include/asm/entry_arch.h      |    4 ++++
 arch/x86/include/asm/hardirq.h         |    2 +-
 arch/x86/include/asm/irq_vectors.h     |    5 +++--
 arch/x86/kernel/cpu/mcheck/threshold.c |    2 +-
 arch/x86/kernel/entry_64.S             |    2 +-
 arch/x86/kernel/irqinit_32.c           |    4 ++++
 arch/x86/kernel/traps.c                |    2 +-
 8 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c1c5ccd..e1c9f77 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -808,7 +808,7 @@ config X86_NEW_MCE
 config X86_MCE_INTEL
 	def_bool y
 	prompt "Intel MCE features"
-	depends on X86_64 && X86_MCE && X86_LOCAL_APIC
+	depends on X86_NEW_MCE && X86_LOCAL_APIC
 	---help---
 	   Additional support for intel specific MCE features such as
 	   the thermal monitor.
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 486c9e9..b2eb9c0 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -56,4 +56,8 @@ BUILD_INTERRUPT(perf_counter_interrupt, LOCAL_PERF_VECTOR)
 BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
 #endif
 
+#ifdef CONFIG_X86_MCE_THRESHOLD
+BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
+#endif
+
 #endif
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 37555e5..922ee7c 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -20,7 +20,7 @@ typedef struct {
 #endif
 #ifdef CONFIG_X86_MCE
 	unsigned int irq_thermal_count;
-# ifdef CONFIG_X86_64
+# ifdef CONFIG_X86_MCE_THRESHOLD
 	unsigned int irq_threshold_count;
 # endif
 #endif
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 3cbd79b..451e24d 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -87,10 +87,11 @@
 #define CALL_FUNCTION_SINGLE_VECTOR	0xfb
 #define THERMAL_APIC_VECTOR		0xfa
 
+#define THRESHOLD_APIC_VECTOR		0xf9
+
 #ifdef CONFIG_X86_32
-/* 0xf8 - 0xf9 : free */
+/* 0xf9 : free */
 #else
-# define THRESHOLD_APIC_VECTOR		0xf9
 # define UV_BAU_MESSAGE			0xf8
 #endif
 
diff --git a/arch/x86/kernel/cpu/mcheck/threshold.c b/arch/x86/kernel/cpu/mcheck/threshold.c
index 23ee9e7..d746df2 100644
--- a/arch/x86/kernel/cpu/mcheck/threshold.c
+++ b/arch/x86/kernel/cpu/mcheck/threshold.c
@@ -17,7 +17,7 @@ static void default_threshold_interrupt(void)
 
 void (*mce_threshold_vector)(void) = default_threshold_interrupt;
 
-asmlinkage void mce_threshold_interrupt(void)
+asmlinkage void smp_threshold_interrupt(void)
 {
 	exit_idle();
 	irq_enter();
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 63276c4..a31a7f2 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1007,7 +1007,7 @@ apicinterrupt INVALIDATE_TLB_VECTOR_START+7 \
 #endif
 
 apicinterrupt THRESHOLD_APIC_VECTOR \
-	threshold_interrupt mce_threshold_interrupt
+	threshold_interrupt smp_threshold_interrupt
 apicinterrupt THERMAL_APIC_VECTOR \
 	thermal_interrupt smp_thermal_interrupt
 
diff --git a/arch/x86/kernel/irqinit_32.c b/arch/x86/kernel/irqinit_32.c
index 98846e0..2512ad9 100644
--- a/arch/x86/kernel/irqinit_32.c
+++ b/arch/x86/kernel/irqinit_32.c
@@ -186,6 +186,10 @@ void __init native_init_IRQ(void)
 	alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 #endif
 
+#ifdef CONFIG_X86_MCE_THRESHOLD
+	alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
+#endif
+
 	if (!acpi_ioapic)
 		setup_irq(2, &irq2);
 
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ad771f1..0d358c8 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -804,7 +804,7 @@ asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
 {
 }
 
-asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void)
+asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
 {
 }
 
-- 
1.6.0.2


  parent reply	other threads:[~2009-05-26 23:21 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-05-26 23:17 x86 Machine check 32bit merge series Andi Kleen
2009-05-26 23:18 ` [PATCH 01/17] x86: MCE: Initial steps to make 64bit mce code 32bit clean Andi Kleen
2009-05-26 23:18   ` [PATCH 02/17] x86: MCE: Implement the PPro bank 0 quirk in the 64bit machine check code Andi Kleen
2009-05-26 23:18   ` [PATCH 03/17] x86: MCE: Port K7 bank 0 quirk to 64bit mce code Andi Kleen
2009-05-26 23:18   ` [PATCH 04/17] x86: MCE: Use a call vector to call the 64bit mce handler Andi Kleen
2009-05-26 23:18   ` [PATCH 05/17] x86: MCE: Rename 64bit mce_dont_init to mce_disabled Andi Kleen
2009-05-26 23:18   ` [PATCH 06/17] x86: MCE: Move mce_disabled option into common 64bit/64bit code Andi Kleen
2009-05-26 23:18   ` [PATCH 07/17] x86: MCE: Remove machine check handler idle notify on 64bit Andi Kleen
2009-05-26 23:18   ` [PATCH 08/17] x86: MCE: Remove oops_begin() use in 64bit machine check Andi Kleen
2009-05-26 23:18   ` [PATCH 09/17] x86: MCE: Remove unused stop/restart_mce on 32bit Andi Kleen
2009-05-26 23:18   ` [PATCH 10/17] x86: MCE: Use 64bit machine check code " Andi Kleen
2009-05-26 23:18   ` [PATCH 11/17] x86: MCE: Deprecate old 32bit machine check code Andi Kleen
2009-05-26 23:18   ` Andi Kleen [this message]
2009-05-26 23:18   ` [PATCH 13/17] x86: MCE: Enable MCE_AMD for 32bit NEW_MCE Andi Kleen
2009-05-26 23:18   ` [PATCH 14/17] x86: MCE: Document new 32bit mcelog requirement in Documentation/Changes Andi Kleen
2009-05-26 23:18   ` [PATCH 15/17] Export add_timer_on for modules Andi Kleen
2009-05-26 23:18   ` [PATCH 16/17] x86: MCE: Add MSR read wrappers for easier error injection Andi Kleen
2009-05-26 23:18   ` [PATCH 17/17] x86: MCE: Add basic error injection infrastructure Andi Kleen

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6dfa191bd595ff969fafb3603ba464254ca895a7.1243377662.git.ak@linux.intel.com \
    --to=andi@firstfloor.org \
    --cc=ak@linux.intel.com \
    --cc=hpa@zytor.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox