From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <anup.patel@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Anup Patel <anup@brainfault.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map()
Date: Sat, 16 May 2020 13:30:31 +0100 [thread overview]
Message-ID: <6e9bf7e1ea3493c63a23c19485f3c644@kernel.org> (raw)
In-Reply-To: <20200516063901.18365-5-anup.patel@wdc.com>
On 2020-05-16 07:39, Anup Patel wrote:
> For multiple PLIC instances, each PLIC can only target a subset of
> CPUs which is represented by "lmask" in the "struct plic_priv".
>
> Currently, the default irq affinity for each PLIC interrupt is all
> online CPUs which is illegal value for default irq affinity when we
> have multiple PLIC instances. To fix this, we now set "lmask" as the
> default irq affinity in for each interrupt in plic_irqdomain_map().
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> ---
> drivers/irqchip/irq-sifive-plic.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c
> index e42fc082ad18..9af5e2fd2574 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -174,6 +174,7 @@ static int plic_irqdomain_map(struct irq_domain
> *d, unsigned int irq,
> irq_domain_set_info(d, irq, hwirq, &priv->chip, d->host_data,
> handle_fasteoi_irq, NULL, NULL);
> irq_set_noprobe(irq);
> + irq_set_affinity(irq, &priv->lmask);
> return 0;
> }
Isn't that a fix? If so, please add a Fixes: tag, as well as a CC to
stable if you think it should be backported.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-05-16 12:30 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-16 6:38 [PATCH 0/4] More improvements for multiple PLICs Anup Patel
2020-05-16 6:38 ` [PATCH 1/4] irqchip/sifive-plic: Setup cpuhp once after current handler is present Anup Patel
2020-05-16 12:11 ` Marc Zyngier
2020-05-16 12:52 ` Anup Patel
2020-05-16 13:30 ` Marc Zyngier
2020-05-16 16:28 ` Anup Patel
2020-05-17 8:02 ` Anup Patel
2020-05-16 6:38 ` [PATCH 2/4] irqchip/sifive-plic: Improve boot prints for multiple PLIC instances Anup Patel
2020-05-16 12:20 ` Marc Zyngier
2020-05-16 12:53 ` Anup Patel
2020-05-16 6:39 ` [PATCH 3/4] irqchip/sifive-plic: Separate irq_chip for muiltiple " Anup Patel
2020-05-16 12:29 ` Marc Zyngier
2020-05-16 13:01 ` Anup Patel
2020-05-16 13:16 ` Marc Zyngier
2020-05-16 16:38 ` Anup Patel
2020-05-18 8:14 ` Marc Zyngier
2020-05-18 9:00 ` Anup Patel
2020-05-16 6:39 ` [PATCH 4/4] irqchip/sifive-plic: Set default irq affinity in plic_irqdomain_map() Anup Patel
2020-05-16 12:30 ` Marc Zyngier [this message]
2020-05-16 12:53 ` Anup Patel
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