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X-CSE-ConnectionGUID: ZJWc3dypR8m48CaFeUVbQg== X-CSE-MsgGUID: p/2RyoykReWQZfefFxc6gQ== X-IronPort-AV: E=McAfee;i="6800,10657,11624"; a="83597603" X-IronPort-AV: E=Sophos;i="6.20,228,1758610800"; d="scan'208";a="83597603" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:19:10 -0800 X-CSE-ConnectionGUID: dabGSDQDRVuZ/CDhmtx9pg== X-CSE-MsgGUID: uzKZ8J/+RZKuiQIlEjQUxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.20,228,1758610800"; d="scan'208";a="198060096" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO localhost) ([10.245.246.1]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Nov 2025 06:19:05 -0800 From: Jani Nikula To: Yaroslav Bolyukin , Ville =?utf-8?B?U3lyasOkbMOk?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Harry Wentland , Leo Li , Rodrigo Siqueira , Alex Deucher , Christian =?utf-8?Q?K=C3=B6nig?= , Wayne Lin , amd-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yaroslav Bolyukin Subject: Re: [PATCH v6 4/7] drm/edid: parse DSC DPP passthru support flag for mode VII timings In-Reply-To: <20251126065126.54016-5-iam@lach.pw> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251126065126.54016-1-iam@lach.pw> <20251126065126.54016-5-iam@lach.pw> Date: Wed, 26 Nov 2025 16:19:02 +0200 Message-ID: <6f88c0111ce7f2a74010ff43a77bdd03f669ffb6@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Wed, 26 Nov 2025, Yaroslav Bolyukin wrote: The commit message goes here. > Signed-off-by: Yaroslav Bolyukin > --- > drivers/gpu/drm/drm_displayid_internal.h | 2 ++ > drivers/gpu/drm/drm_edid.c | 12 ++++++++---- > include/drm/drm_modes.h | 10 ++++++++++ > 3 files changed, 20 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/drm_displayid_internal.h b/drivers/gpu/drm/drm_displayid_internal.h > index 72f107ae832f..724174b429f2 100644 > --- a/drivers/gpu/drm/drm_displayid_internal.h > +++ b/drivers/gpu/drm/drm_displayid_internal.h > @@ -97,6 +97,7 @@ struct displayid_header { > u8 ext_count; > } __packed; > > +#define DISPLAYID_BLOCK_REV GENMASK(2, 0) > struct displayid_block { > u8 tag; > u8 rev; > @@ -125,6 +126,7 @@ struct displayid_detailed_timings_1 { > __le16 vsw; > } __packed; > > +#define DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT BIT(3) > struct displayid_detailed_timing_block { > struct displayid_block base; > struct displayid_detailed_timings_1 timings[]; > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c > index 348aa31aea1b..72a94b1713e2 100644 > --- a/drivers/gpu/drm/drm_edid.c > +++ b/drivers/gpu/drm/drm_edid.c > @@ -6792,8 +6792,8 @@ static void update_display_info(struct drm_connector *connector, > } > > static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, > - const struct displayid_detailed_timings_1 *timings, > - bool type_7) > + const struct displayid_block *block, > + const struct displayid_detailed_timings_1 *timings) > { > struct drm_display_mode *mode; > unsigned int pixel_clock = (timings->pixel_clock[0] | > @@ -6809,11 +6809,16 @@ static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *d > unsigned int vsync_width = le16_to_cpu(timings->vsw) + 1; > bool hsync_positive = le16_to_cpu(timings->hsync) & (1 << 15); > bool vsync_positive = le16_to_cpu(timings->vsync) & (1 << 15); > + bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; > > mode = drm_mode_create(dev); > if (!mode) > return NULL; > > + if (type_7 && FIELD_GET(DISPLAYID_BLOCK_REV, block->rev) >= 1) > + mode->dsc_passthrough_timings_support = > + !!(block->rev & DISPLAYID_BLOCK_PASSTHROUGH_TIMINGS_SUPPORT); The !! and parentheses are superfluous. > + > /* resolution is kHz for type VII, and 10 kHz for type I */ > mode->clock = type_7 ? pixel_clock : pixel_clock * 10; > mode->hdisplay = hactive; > @@ -6846,7 +6851,6 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector, > int num_timings; > struct drm_display_mode *newmode; > int num_modes = 0; > - bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; > /* blocks must be multiple of 20 bytes length */ > if (block->num_bytes % 20) > return 0; > @@ -6855,7 +6859,7 @@ static int add_displayid_detailed_1_modes(struct drm_connector *connector, > for (i = 0; i < num_timings; i++) { > struct displayid_detailed_timings_1 *timings = &det->timings[i]; > > - newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); > + newmode = drm_mode_displayid_detailed(connector->dev, block, timings); > if (!newmode) > continue; > > diff --git a/include/drm/drm_modes.h b/include/drm/drm_modes.h > index b9bb92e4b029..312e5c03af9a 100644 > --- a/include/drm/drm_modes.h > +++ b/include/drm/drm_modes.h > @@ -417,6 +417,16 @@ struct drm_display_mode { > */ > enum hdmi_picture_aspect picture_aspect_ratio; > > + /** > + * @dsc_passthrough_timing_support: > + * > + * Indicates whether this mode timing descriptor is supported > + * with specific target DSC bits per pixel only. > + * > + * VESA vendor-specific data block shall exist with the relevant > + * DSC bits per pixel declaration when this flag is set to true. > + */ > + bool dsc_passthrough_timings_support; > }; > > /** -- Jani Nikula, Intel