From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9573202630; Tue, 12 Nov 2024 15:49:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731426578; cv=none; b=sqc4nHfYV0zXuvIMfqEPWVhjef6rKvndNdafMKtZZ5xHEqdW/sHIE+bXE67zSZhZpkp21cVH7LxD/0RyJyXejqfoVYJy3qXQIdsa9dv7ngZ7rg9A+wUmwFwZCX4f4YXBG7hH1Pw7Z903GkMcCNFCzmvtfaOU/Kh+XL1Lzo31kPQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731426578; c=relaxed/simple; bh=JPvp3Mh/bQjUYQkmm8hWLGL1nUaZ5fMwHjXvQSZsZYo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ll8EE8V18W8UwEBwjVCn4+QpfbP0jygg/pfGLZEGjz7SIbQFtQwfZdhT34Gw6LGPL4cmaGrK/Ds3Is6IxzcNue8E0v8U3pgHF1/jI3hhiH8jc7eE6sfyxjeYZfenzoL2puT+5x0UiLhcGhkbOwpbXT70zihT01JeIZgiP9n0OuM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Do/7rYUs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Do/7rYUs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 267EAC4CECD; Tue, 12 Nov 2024 15:49:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1731426577; bh=JPvp3Mh/bQjUYQkmm8hWLGL1nUaZ5fMwHjXvQSZsZYo=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Do/7rYUspPeEoWMaeACCaJadOiUwHw3Kl4Zt5vQPquRqdxl0MH71LUywsjHIbnWi/ hVsvPI7xTJ+iGVrd1kkonTi+JmIU2LhSSteoh/gUJaYCXQsq1D0bQsllo4MZYipyd7 AY8+OpRMStTHprdVpkQ+LWAJuoneLKaU8YKUDYA3ESkvtVzhxHjBX/6IDeL9W8PjH/ WVfp51P3KGpoF9XXkoDt0Gmp4zWhut0Ja9mudv1cq0+/jvFaC99FcTt1T6UYwg/BbL ie/vQh7A7ZffM1Zn5yjCvMVxYMxYpegnD8M8ybLiFYlkslQ7nzJ1BS6RC820PvGMGy Ibjy7Thz1wlag== Date: Tue, 12 Nov 2024 09:49:34 -0600 From: Bjorn Andersson To: Krishna chaitanya chundru Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/6] arm64: dts: qcom: qcs6490-rb3gen2: Add node for qps615 Message-ID: <6lfxpzpfpfb2s2rhbf3ch4rgyegw6cehfbrj26sqodzr2vfi4q@hgc3ahuulwqv> References: <20241112-qps615_pwr-v3-0-29a1e98aa2b0@quicinc.com> <20241112-qps615_pwr-v3-2-29a1e98aa2b0@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241112-qps615_pwr-v3-2-29a1e98aa2b0@quicinc.com> On Tue, Nov 12, 2024 at 08:31:34PM +0530, Krishna chaitanya chundru wrote: > Add QPS615 PCIe switch node which has 3 downstream ports and in one > downstream port two embedded ethernet devices are present. > > Power to the QPS615 is supplied through two LDO regulators, controlled > by two GPIOs, these are added as fixed regulators. And the QPS615 is > configured through i2c. > > Signed-off-by: Krishna chaitanya chundru Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 115 +++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- > 2 files changed, 116 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > index 0d45662b8028..0e890841b600 100644 > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > @@ -202,6 +202,30 @@ vph_pwr: vph-pwr-regulator { > regulator-min-microvolt = <3700000>; > regulator-max-microvolt = <3700000>; > }; > + > + vdd_ntn_0p9: regulator-vdd-ntn-0p9 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_0P9"; > + gpio = <&pm8350c_gpios 2 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <899400>; > + regulator-max-microvolt = <899400>; > + enable-active-high; > + pinctrl-0 = <&ntn_0p9_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <4300>; > + }; > + > + vdd_ntn_1p8: regulator-vdd-ntn-1p8 { > + compatible = "regulator-fixed"; > + regulator-name = "VDD_NTN_1P8"; > + gpio = <&pm8350c_gpios 3 GPIO_ACTIVE_HIGH>; > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + enable-active-high; > + pinctrl-0 = <&ntn_1p8_en>; > + pinctrl-names = "default"; > + regulator-enable-ramp-delay = <10000>; > + }; > }; > > &apps_rsc { > @@ -684,6 +708,75 @@ &mdss_edp_phy { > status = "okay"; > }; > > +&pcie1_port { > + pcie@0,0 { > + compatible = "pci1179,0623"; > + reg = <0x10000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x2 0xff>; > + > + vddc-supply = <&vdd_ntn_0p9>; > + vdd18-supply = <&vdd_ntn_1p8>; > + vdd09-supply = <&vdd_ntn_0p9>; > + vddio1-supply = <&vdd_ntn_1p8>; > + vddio2-supply = <&vdd_ntn_1p8>; > + vddio18-supply = <&vdd_ntn_1p8>; > + > + i2c-parent = <&i2c0 0x77>; > + > + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; > + > + pcie@1,0 { > + reg = <0x20800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x3 0xff>; > + }; > + > + pcie@2,0 { > + reg = <0x21000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + > + device_type = "pci"; > + ranges; > + bus-range = <0x4 0xff>; > + }; > + > + pcie@3,0 { > + reg = <0x21800 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + bus-range = <0x5 0xff>; > + > + pcie@0,0 { > + reg = <0x50000 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + }; > + > + pcie@0,1 { > + reg = <0x50100 0x0 0x0 0x0 0x0>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges; > + }; > + }; > + }; > +}; > + > &pmk8350_rtc { > status = "okay"; > }; > @@ -812,6 +905,28 @@ lt9611_rst_pin: lt9611-rst-state { > }; > }; > > +&pm8350c_gpios { > + ntn_0p9_en: ntn-0p9-en-state { > + pins = "gpio2"; > + function = "normal"; > + > + bias-disable; > + input-disable; > + output-enable; > + power-source = <0>; > + }; > + > + ntn_1p8_en: ntn-1p8-en-state { > + pins = "gpio3"; > + function = "normal"; > + > + bias-disable; > + input-disable; > + output-enable; > + power-source = <0>; > + }; > +}; > + > &tlmm { > lt9611_irq_pin: lt9611-irq-state { > pins = "gpio24"; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 3d8410683402..82434f085ff0 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -2279,7 +2279,7 @@ pcie1: pcie@1c08000 { > > status = "disabled"; > > - pcie@0 { > + pcie1_port: pcie@0 { > device_type = "pci"; > reg = <0x0 0x0 0x0 0x0 0x0>; > bus-range = <0x01 0xff>; > > -- > 2.34.1 >