Re: [PATCH 2/2] dt-bindings: riscv: fix single letter canonical order

Heiko Stübner
2022-11-24T13:42:39Z

Am Donnerstag, 24. November 2022, 14:04:41 CET schrieb Conor Dooley:
> I used the wikipedia table for ordering extensions when updating the
> pattern here in foo.

^ foo? :-)

> Unfortunately that table did not match canonical order, as defined by
> the RISC-V ISA Manual, which defines extension ordering in (what is
> currently) Table 41, "Standard ISA extension names". Fix things up by
> re-sorting v (vector) and adding p (packed-simd) & j (dynamic
> languages). The e (reduced integer) and g (general) extensions are still
> intentionally left out.
>
> Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5
> Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators")
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

So I have compared the new pattern to the isa manual,
and it looks like the order checks out, so

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index e80c967a4fa4..b7462ea2dbe4 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -80,7 +80,7 @@ properties:
> insensitive, letters in the riscv,isa string must be all
> lowercase to simplify parsing.
> $ref: "/schemas/types.yaml#/definitions/string"
> - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
> + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
>
> # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
> timebase-frequency: false
>