From: "David E. Box" <david.e.box@linux.intel.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
platform-driver-x86@vger.kernel.org,
rajvi.jingar@linux.intel.com
Subject: Re: [PATCH 10/11] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P
Date: Tue, 26 Sep 2023 17:20:19 -0700 [thread overview]
Message-ID: <7106078fedb5a58d8ca1e8dfb10245929d4dc269.camel@linux.intel.com> (raw)
In-Reply-To: <a2f52dca-ffaf-31b0-c281-48fc193e6552@linux.intel.com>
On Tue, 2023-09-26 at 19:03 +0300, Ilpo Järvinen wrote:
> On Fri, 22 Sep 2023, David E. Box wrote:
>
> > From: Xi Pardee <xi.pardee@intel.com>
> >
> > Add support to read the low power mode requirements for Meteor Lake M and
> > Meteor Lake P.
> >
> > Signed-off-by: Xi Pardee <xi.pardee@intel.com>
> > Signed-off-by: David E. Box <david.e.box@linux.intel.com>
> > ---
> > drivers/platform/x86/intel/pmc/mtl.c | 39 +++++++++++++++++++++++-----
> > 1 file changed, 33 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/platform/x86/intel/pmc/mtl.c
> > b/drivers/platform/x86/intel/pmc/mtl.c
> > index 780874142a90..c2ac50cfdd51 100644
> > --- a/drivers/platform/x86/intel/pmc/mtl.c
> > +++ b/drivers/platform/x86/intel/pmc/mtl.c
> > @@ -11,6 +11,13 @@
> > #include <linux/pci.h>
> > #include "core.h"
> >
> > +/* PMC SSRAM PMT Telemetry GUIDS */
> > +#define SOCP_LPM_REQ_GUID 0x2625030
> > +#define IOEM_LPM_REQ_GUID 0x4357464
> > +#define IOEP_LPM_REQ_GUID 0x5077612
> > +
> > +static const u8 MTL_LPM_REG_INDEX[] = {0, 4, 5, 6, 8, 9, 10, 11, 12, 13,
> > 14, 15, 16, 20};
> > +
> > /*
> > * Die Mapping to Product.
> > * Product SOCDie IOEDie PCHDie
> > @@ -465,6 +472,7 @@ const struct pmc_reg_map mtl_socm_reg_map = {
> > .lpm_sts = mtl_socm_lpm_maps,
> > .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
> > .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
> > + .lpm_reg_index = MTL_LPM_REG_INDEX,
> > };
> >
> > const struct pmc_bit_map mtl_ioep_pfear_map[] = {
> > @@ -782,6 +790,13 @@ const struct pmc_reg_map mtl_ioep_reg_map = {
> > .ltr_show_sts = mtl_ioep_ltr_show_map,
> > .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
> > .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
> > + .lpm_num_maps = ADL_LPM_NUM_MAPS,
> > + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
> > + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
> > + .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
> > + .lpm_en_offset = MTL_LPM_EN_OFFSET,
> > + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
> > + .lpm_reg_index = MTL_LPM_REG_INDEX,
> > };
> >
> > const struct pmc_bit_map mtl_ioem_pfear_map[] = {
> > @@ -922,6 +937,13 @@ const struct pmc_reg_map mtl_ioem_reg_map = {
> > .ltr_show_sts = mtl_ioep_ltr_show_map,
> > .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
> > .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
> > + .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
> > + .lpm_num_maps = ADL_LPM_NUM_MAPS,
> > + .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
> > + .lpm_en_offset = MTL_LPM_EN_OFFSET,
> > + .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
> > + .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
> > + .lpm_reg_index = MTL_LPM_REG_INDEX,
> > };
> >
> > #define PMC_DEVID_SOCM 0x7e7f
> > @@ -929,16 +951,19 @@ const struct pmc_reg_map mtl_ioem_reg_map = {
> > #define PMC_DEVID_IOEM 0x7ebf
> > static struct pmc_info mtl_pmc_info_list[] = {
> > {
> > - .devid = PMC_DEVID_SOCM,
> > - .map = &mtl_socm_reg_map,
> > + .guid = SOCP_LPM_REQ_GUID,
> > + .devid = PMC_DEVID_SOCM,
> > + .map = &mtl_socm_reg_map,
> > },
> > {
> > - .devid = PMC_DEVID_IOEP,
> > - .map = &mtl_ioep_reg_map,
> > + .guid = IOEP_LPM_REQ_GUID,
> > + .devid = PMC_DEVID_IOEP,
> > + .map = &mtl_ioep_reg_map,
> > },
> > {
> > - .devid = PMC_DEVID_IOEM,
> > - .map = &mtl_ioem_reg_map
> > + .guid = IOEM_LPM_REQ_GUID,
> > + .devid = PMC_DEVID_IOEM,
> > + .map = &mtl_ioem_reg_map
> > },
> > {}
> > };
> > @@ -1012,5 +1037,7 @@ int mtl_core_init(struct pmc_dev *pmcdev)
> > dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
> > pmc_core_send_ltr_ignore(pmcdev, 3);
> >
> > + ret = pmc_core_ssram_get_lpm_reqs(pmcdev);
> > +
>
> Unused return value??
Good catch.
>
> > return 0;
> > }
> >
>
next prev parent reply other threads:[~2023-09-27 1:08 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-22 21:30 [PATCH 00/11] intel_pmc: Add telemetry API to read counters David E. Box
2023-09-22 21:30 ` [PATCH 01/11] platform/x86/intel/vsec: Add intel_vsec_register David E. Box
2023-09-26 14:17 ` Ilpo Järvinen
2023-09-26 23:51 ` David E. Box
2023-09-22 21:30 ` [PATCH 02/11] platform/x86/intel/vsec: Add base address field David E. Box
2023-09-26 14:39 ` Ilpo Järvinen
2023-09-22 21:30 ` [PATCH 03/11] platform/x86/intel/pmt: Add header to struct intel_pmt_entry David E. Box
2023-09-26 14:43 ` Ilpo Järvinen
2023-09-22 21:30 ` [PATCH 04/11] platform/x86/intel/pmt: telemetry: Export API to read telemetry David E. Box
2023-09-26 15:40 ` Ilpo Järvinen
2023-09-26 23:59 ` David E. Box
2023-09-22 21:30 ` [PATCH 05/11] platform/x86:intel/pmc: Move get_low_power_modes function David E. Box
2023-09-26 15:56 ` Ilpo Järvinen
2023-09-27 0:16 ` David E. Box
2023-09-22 21:30 ` [PATCH 06/11] platform/x86/intel/pmc: Split pmc_core_ssram_get_pmc() David E. Box
2023-09-22 21:30 ` [PATCH 07/11] platform/x86/intel/pmc: Find and register PMC telemetry entries David E. Box
2023-09-22 21:30 ` [PATCH 08/11] platform/x86/intel/pmc: Display LPM requirements for multiple PMCs David E. Box
2023-09-22 21:30 ` [PATCH 09/11] platform/x86/intel/pmc: Retrieve LPM information using Intel PMT David E. Box
2023-09-26 16:07 ` Ilpo Järvinen
2023-09-22 21:30 ` [PATCH 10/11] platform/x86/intel/pmc: Read low power mode requirements for MTL-M and MTL-P David E. Box
2023-09-26 16:03 ` Ilpo Järvinen
2023-09-27 0:20 ` David E. Box [this message]
2023-09-22 21:30 ` [PATCH 11/11] platform/x86/intel/pmc: Add debug attribute for Die C6 counter David E. Box
2023-09-26 16:11 ` Ilpo Järvinen
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