From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753475AbbGJHuV (ORCPT ); Fri, 10 Jul 2015 03:50:21 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:37075 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752890AbbGJHuO (ORCPT ); Fri, 10 Jul 2015 03:50:14 -0400 X-AuditID: cbfee68e-f79c56d000006efb-90-559f7934ab60 Date: Fri, 10 Jul 2015 07:50:12 +0000 (GMT) From: Sarbojit Ganguly Subject: [PATCH] arm: Adding support for atomic half word exchange To: Sarbojit Ganguly , Arnd Bergmann Cc: Raghavendra K T , "linux-arm-kernel@lists.infradead.org" , SUNEEL KUMAR SURIMANI , VIKRAM MUPPARTHI , "tglx@linutronix.de" , "mingo@redhat.com" , "hpa@zytor.com" , "peterz@infradead.org" , "Waiman.Long@hp.com" , "oleg@redhat.com" , "linux-kernel@vger.kernel.org" , SHARAN ALLUR , "torvalds@linux-foundation.org" Reply-to: ganguly.s@samsung.com MIME-version: 1.0 X-MTR: 20150710065555696@ganguly.s Msgkey: 20150710065555696@ganguly.s X-EPLocale: en_US.windows-1252 X-Priority: 3 X-EPWebmail-Msg-Type: personal X-EPWebmail-Reply-Demand: 0 X-EPApproval-Locale: X-EPHeader: ML X-MLAttribute: X-RootMTR: 20150703142807952@ganguly.s X-ParentMTR: 20150703143444385@ganguly.s X-ArchiveUser: X-CPGSPASS: Y X-ConfirmMail: N,general Content-type: text/plain; charset=windows-1252 MIME-version: 1.0 Message-id: <710840938.569501436514608029.JavaMail.weblogic@ep2mlwas06b> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrCIsWRmVeSWpSXmKPExsWyRsSkStekcn6owYe75haXd81hc2D0+LxJ LoAxissmJTUnsyy1SN8ugSvj/4aDzAWf+Cr2f7nH3sC4h6+LkYNDSEBFom9SRBcjJ4eEgInE /ms/GSFsMYkL99azdTFyAZUsZZRY1PmPDaboZVMTM4gtJDCHUeLTD3kQm0VAVWLPtlVgzWwC +hKn979kArGFBZwkHrT2gfWKCARKfDp5lgVkKLPANFaJ3UdmskAMkpdof7EdrIFXQFDi5Mwn LBDLlCSa7k9lhIgrSxztb4SKy0ksmXqZCcLmlZjR/hQuPu3rGmYIW1ri/KwNcN8s/v4YKs4v cez2DqheAYmpZw5C1ahLTFx7AapGU+Luo/uMMPW7Ti1nhtnVsPE3O4QtIbG15QkriM0soCgx pfshO4RtIHFk0RxWdL/wCnhIbFz6H2pvL4fE7c1yExiVZiEpm4Vk1Cwko5DVLGBkWcUomlqQ XFCclF5kpFecmFtcmpeul5yfu4kRmBhO/3vWt4Px5gHrQ4wCHIxKPLwBbPNDhVgTy4orcw8x mgLjaSKzlGhyPjD95JXEGxqbGVmYmpgaG5lbmimJ8yZI/QwWEkhPLEnNTk0tSC2KLyrNSS0+ xMjEwSnVwDi/Lvvkmh1LCovLo2d9lNxRft4r6c/ZNeqrdKxZatP7HoZXXp7UW8O6R/DDzZ4J OcdL2NYdPXL8b5Vz67Wieb+/yKZfjNdYZLVSRCGa1/HB0WTjhlmvt0vwbNVn9LhzxsfrjXvA CeaHeQtl9FIXxssvb2c4NU9I1WDXq0lCLGnv4r1cjzWqP1NiKc5INNRiLipOBADmXpvqBwMA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGKsWRmVeSWpSXmKPExsVy+t/tXl2TyvmhBl+m6Vhc3jWHzYHR4/Mm uQDGqDSbjNTElNQihdS85PyUzLx0WyXv4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKCh SgpliTmlQKGAxOJiJX07m6L80pJUhYz84hJbpWhDcyM9IwM9UyM9Q9NYK0MDAyNToJqEtIz/ Gw4yF3ziq9j/5R57A+Mevi5GDg4hARWJvkkRXYycHBICJhIvm5qYIWwxiQv31rOB2EICcxgl Pv2QB7FZBFQl9mxbxQhiswnoS5ze/5IJxBYWcJJ40NoHVi8iECjx6eRZli5GLg5mgWmsEruP zGSBGCQv0f5iO1gDr4CgxMmZT1gglilJNN2fyggRV5Y42t8IFZeTWDL1MhOEzSsxo/0pXHza 1zVQh0pLnJ+1gRHm6MXfH0PF+SWO3d4B1SsgMfXMQagadYmJay9A1WhK3H10nxGmftep5cww uxo2/maHsCUktrY8YQWxmQUUJaZ0P2SHsA0kjiyaw4ruF14BD4mNS/8zTWCUnYUkNQtJ+ywk 7chqFjCyrGIUTS1ILihOSq8w0StOzC0uzUvXS87P3cQITkPPluxgbLhgfYhRgINRiYc3gG1+ qBBrYllxZe4hRgkOZiURXn4JoBBvSmJlVWpRfnxRaU5q8SFGU2C0TWSWEk3OB6bIvJJ4Q2MT c1NjUwsDQ3NzMyVx3v/nckOEBNITS1KzU1MLUotg+pg4OKUaGI3DZBwq//X9suE4/LVkTUGH 1Xz90l/OMwu6ZGWVbphmdjPcunLx4cbCt2yTQs9G/BIKLGbs0v1q8FfIK3Dq4T2xXAVCs5ct //n9iGag6flm9Q/LRWfXTDoZq3h4yZRuG+GwHwFXeoSa3vacEpP3Noidl/Tb5WaFQWZ3rNXM d4+2T5vXyVt7VImlOCPRUIu5qDgRAJkHlV1ZAwAA DLP-Filter: Pass X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t6A7oOfV006035 Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word, here is a small modification to __xchg() code to support the exchange. ARMv6 and lower does not have support for LDREXH, so we need to make sure things do not break when we're compiling on ARMv6. Signed-off-by: Sarbojit Ganguly --- arch/arm/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 1692a05..547101d 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -50,6 +50,24 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size : "r" (x), "r" (ptr) : "memory", "cc"); break; +#if !defined (CONFIG_CPU_V6) + /* + * Halfword exclusive exchange + * This is new implementation as qspinlock + * wants 16 bit atomic CAS. + * This is not supported on ARMv6. + */ + case 2: + asm volatile("@ __xchg2\n" + "1: ldrexh %0, [%3]\n" + " strexh %1, %2, [%3]\n" + " teq %1, #0\n" + " bne 1b" + : "=&r" (ret), "=&r" (tmp) + : "r" (x), "r" (ptr) + : "memory", "cc"); + break; +#endif case 4: asm volatile("@ __xchg4\n" "1: ldrex %0, [%3]\n" -- Sarbojit{.n++%ݶw{.n+{G{ayʇڙ,jfhz_(階ݢj"mG?&~iOzv^m ?I