From: Raphael Gault <raphael.gault@arm.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Robin Murphy <robin.murphy@arm.com>,
mark.rutland@arm.com, catalin.marinas@arm.com,
will.deacon@arm.com, linux-kernel@vger.kernel.org,
acme@kernel.org, mingo@redhat.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC 4/7] arm64: pmu: Add function implementation to update event index in userpage.
Date: Wed, 29 May 2019 13:39:51 +0100 [thread overview]
Message-ID: <7178bdfe-92d0-22b5-60cf-b67a976dc6a2@arm.com> (raw)
In-Reply-To: <20190529123256.GT2623@hirez.programming.kicks-ass.net>
Hi Peter,
On 5/29/19 1:32 PM, Peter Zijlstra wrote:
> On Wed, May 29, 2019 at 01:25:46PM +0100, Raphael Gault wrote:
>> Hi Robin, Hi Peter,
>>
>> On 5/29/19 11:50 AM, Robin Murphy wrote:
>>> On 29/05/2019 11:46, Raphael Gault wrote:
>>>> Hi Peter,
>>>>
>>>> On 5/29/19 10:46 AM, Peter Zijlstra wrote:
>>>>> On Tue, May 28, 2019 at 04:03:17PM +0100, Raphael Gault wrote:
>>>>>> +static int armv8pmu_access_event_idx(struct perf_event *event)
>>>>>> +{
>>>>>> + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
>>>>>> + return 0;
>>>>>> +
>>>>>> + /*
>>>>>> + * We remap the cycle counter index to 32 to
>>>>>> + * match the offset applied to the rest of
>>>>>> + * the counter indeces.
>>>>>> + */
>>>>>> + if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
>>>>>> + return 32;
>>>>>> +
>>>>>> + return event->hw.idx;
>>>>>
>>>>> Is there a guarantee event->hw.idx is never 0? Or should you, just like
>>>>> x86, use +1 here?
>>>>>
>>>>
>>>> You are right, I should use +1 here. Thanks for pointing that out.
>>>
>>> Isn't that already the case though, since we reserve index 0 for the
>>> cycle counter? I'm looking at ARMV8_IDX_TO_COUNTER() here...
>>>
>>
>> Well the current behaviour is correct and takes care of the zero case with
>> the ARMV8_IDX_CYCLE_COUNTER check. But using ARMV8_IDX_TO_COUNTER() and add
>> 1 would also work. However this seems indeed redundant with the current
>> value held in event->hw.idx.
>
> Note that whatever you pick now will become ABI. Also note that the
> comment/pseudo-code in perf_event_mmap_page suggests to use idx-1 for
> the actual hardware access.
>
Indeed that's true. As for the pseudo-code in perf_event_mmap_page. It
is compatible with what I do here. The two approach are only different
in form but it is in both case necessary to subtract 1 on the returned
value in order to access the correct hardware counter.
Thank you,
--
Raphael Gault
next prev parent reply other threads:[~2019-05-29 12:39 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-28 15:03 [RFC V2 0/7] arm64: Enable access to pmu registers by user-space Raphael Gault
2019-05-28 15:03 ` [RFC 1/7] perf: arm64: Compile tests unconditionally Raphael Gault
2019-05-28 15:19 ` Arnaldo Carvalho de Melo
2019-05-28 16:16 ` Mark Rutland
2019-05-28 15:03 ` [RFC 2/7] perf: arm64: Add test to check userspace access to hardware counters Raphael Gault
2019-05-28 15:03 ` [RFC 3/7] perf: arm64: Use rseq to test userspace access to pmu counters Raphael Gault
2019-05-28 15:03 ` [RFC 4/7] arm64: pmu: Add function implementation to update event index in userpage Raphael Gault
2019-05-29 9:46 ` Peter Zijlstra
2019-05-29 10:46 ` Raphael Gault
2019-05-29 10:50 ` Robin Murphy
2019-05-29 12:25 ` Raphael Gault
2019-05-29 12:32 ` Peter Zijlstra
2019-05-29 12:39 ` Raphael Gault [this message]
2019-05-28 15:03 ` [RFC 5/7] arm64: pmu: Add hook to handle pmu-related undefined instructions Raphael Gault
2019-05-29 9:45 ` Peter Zijlstra
2019-05-28 15:03 ` [RFC 6/7] arm64: perf: Enable pmu counter direct access for perf event on armv8 Raphael Gault
2019-05-28 15:03 ` [RFC 7/7] Documentation: arm64: Document PMU counters access from userspace Raphael Gault
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